A 125MHz 8b digital-to-phase converter

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Chou, Ju Ming ^a   Hsieh, Yu Tang ^a   Wu, Jieh Tsorng ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; ELECTRIC WAVEFORMS; INTERPOLATION; LOGIC CIRCUITS; OSCILLATORS (ELECTRONIC); PHASE LOCKED LOOPS; PHASE SHIFT; RESISTORS;

DELAY LOCKED LOOP; DIGITAL-TO-PHASE CONVERTER; MULTI-STAGE RING OSCILLATOR; PHASE INTERPOLATOR;

ELECTRIC CONVERTERS;

EID: 0037630665     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. S. Sidoropoulos and M. A. Horowitz, "A Semidigital Dual Delay-Locked Loop," IEEE Journal of Solid-State Circuits, vol. 32, pp. 1683-1692, November 1997.
2. 2," IEEE Journal of Solid-State Circuits, vol. 32, pp. 1887-1895, December 1997.
3. J. G. Maneatis, "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques," IEEE Journal of Solid-State Circuits, vol. 31, pp. 1723-1732, November 1996.
4. T. H. Lee, K. S. Donnelly, J. T. C. Ho, J. Zerbe, M. G. Johnson, and T. Ishikawa, "A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM," IEEE Journal of Solid-State Circuits, vol. 29, pp. 1491-1496, December 1994.