In-line interrupt handling and lock-up free translation lookaside buffers (TLBs)

IEEE Transactions on Computers

Volumn 55, Issue 5, 2006, Pages 559-574

  Jaleel, Aamer ^a   Jacob, Bruce ^a  

^a UNIVERSITY OF MARYLAND   (United States)

Author keywords

Exception handlers; In line interrupt; Lock up free; Performance modeling; Precise interrupts; Reorder buffer (ROB); Translation lookaside buffers (TLBs)

Indexed keywords

DATA STORAGE EQUIPMENT; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PIPELINE PROCESSING SYSTEMS;

CENTRAL PROCESSING UNIT (CPU); IN-LINE INTERRUPT; LOCK-UP FREE; PERFORMANCE MODELING; PRECISE INTERRUPTS; REORDER-BUFFER (ROB); TRANSLATION LOOK-ASIDE BUFFER (TLB);

BUFFER STORAGE;

EID: 33645805012     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2006.77     Document Type: Article

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