On the gate capacitance limits of nanoscale DG and FD SOI MOSFETs

IEEE Transactions on Electron Devices

Volumn 53, Issue 4, 2006, Pages 753-758

  Ge, Lixin ^a   Gámiz, Francisco ^b   Workman, Glenn O ^a   Veeraraghavan, Surya ^a  

^a FREESCALE SEMICONDUCTOR INC   (United States)

^b UNIVERSITY OF GRANADA   (Spain)

Author keywords

CMOS modeling; Double gate (DG) MOSFETs; Energy quantization; Fully depleted silicon on insulator (FD SOI); Gate capacitance; Inversion layer screening

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); NUMERICAL ANALYSIS; POISSON EQUATION; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MODELS; SILICON ON INSULATOR TECHNOLOGY;

CARRIER-ENERGY QUANTIZATION; DOUBLE-GATE (DG) MOSFETS; FULLY DEPLETED SILICON-ON-INSULATOR (FD/SOI); GATE CAPACITANCE; INVERSION-LAYER SCREENING;

MOSFET DEVICES;

EID: 33645771671     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.871412     Document Type: Article

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