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Volumn 6050, Issue , 2005, Pages

The need of DNA computing: Reversible designs of adders and multipliers using Fredkin gate

Author keywords

DNA Computing; Reversible Adders and Multipliers; Reversible Logic

Indexed keywords

ADDERS; COMPUTER HARDWARE; LOGIC DESIGN; NANOTECHNOLOGY; QUANTUM THEORY;

EID: 33645065366     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.652660     Document Type: Conference Paper
Times cited : (15)

References (17)
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    • Landauer, R.1
  • 2
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    • November
    • C.H. Bennett, "Logical Reversibility of Computation", IBM J. Research and Development, pp. 525-532, November 1973.
    • (1973) IBM J. Research and Development , pp. 525-532
    • Bennett, C.H.1
  • 4
    • 0004245012 scopus 로고
    • Reversible computing
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    • (1980) Tech Memo , vol.MIT-LCS-TM-151
    • Toffoli, T.1
  • 5
    • 23844558805 scopus 로고    scopus 로고
    • Simulating the Fredkin Gate with energy {based P systems}
    • Alberto LEPORATI, Claudio ZANDRON, Giancarlo MAURI," Simulating the Fredkin Gate with Energy {Based P Systems", Journal of Universal Computer Science,Volume 10,Issue 5,pp 600-619.
    • Journal of Universal Computer Science , vol.10 , Issue.5 , pp. 600-619
    • Leporati, A.1    Zandron, C.2    Mauri, G.3
  • 7
    • 33845188112 scopus 로고    scopus 로고
    • Novel reversible "TSG" gate and its application for designing reversible carry look ahead adder and other adder architectures
    • Singapore, October 24-26 (Accepted)
    • Himanshu Thapliyal and M.B Srinivas, "Novel Reversible "TSG" Gate and Its Application for Designing Reversible Carry Look Ahead Adder and Other Adder Architectures", Tenth Asia-Pacific Computer Systems Architecture Conference (ACSAC05), Singapore, October 24-26, 2005 (Accepted).
    • (2005) Tenth Asia-Pacific Computer Systems Architecture Conference (ACSAC05)
    • Thapliyal, H.1    Srinivas, M.B.2
  • 12
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    • A method for speed optimized partial productreduction and generation of fast parallel multipliers using and alghoritmic approach
    • March
    • V.G. Oklobdzija, D. Villeger, S. S. Liu, "A Method for Speed Optimized Partial ProductReduction and Generation of Fast Parallel Multipliers Using and Alghoritmic Approach", IEEE Transaction on Computers, Vol. 45, No 3, March 1996.
    • (1996) IEEE Transaction on Computers , vol.45 , Issue.3
    • Oklobdzija, V.G.1    Villeger, D.2    Liu, S.S.3
  • 14
    • 84894279293 scopus 로고    scopus 로고
    • High-speed VLSI arithmetic units: Adders and multipliers
    • Book Chapter, Book edited by A. Chandrakasan, IEEE Press
    • V. Oklobdzija, "High-Speed VLSI Arithmetic Units: Adders and Multipliers", in "Design of High-Performance Microprocessor Circuits", Book Chapter, Book edited by A. Chandrakasan, IEEE Press, 2000.
    • (2000) Design of High-performance Microprocessor Circuits
    • Oklobdzija, V.1
  • 17
    • 0035247682 scopus 로고    scopus 로고
    • A 600-MHz 54 × 54-bit multiplier with rectangular-styled wallace tree
    • February
    • Niichi Itoh, Yuka Naemura, Hiroshi Makino, Yasunobu Nakase, Tsutomu Yoshihara, and Yasutaka Horiba, "A 600-MHz 54 × 54-bit Multiplier with Rectangular-Styled Wallace Tree", JSSC, vol.36, no. 2, February 2001.
    • (2001) JSSC , vol.36 , Issue.2
    • Itoh, N.1    Naemura, Y.2    Makino, H.3    Nakase, Y.4    Yoshihara, T.5    Horiba, Y.6


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.