Compact 54 × 54-bit multiplier with improved wallace-tree structure

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1999, Pages 15-16

  Itoh, Niichi ^a   Naemura, Yuka ^a   Makino, Hiroshi ^a   Nakase, Yasunobu ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COSTS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; MULTIMEDIA SYSTEMS; THREE DIMENSIONAL COMPUTER GRAPHICS;

BOOTH ALGORITHMS; COMPACT MULTIPLIER; HIGH SPEED FLOATING POINT; HIGH SPEED MULTIPLIER; WALLACE TREE STRUCTURE;

MULTIPLYING CIRCUITS;

EID: 0033280552     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)