메뉴 건너뛰기




Volumn , Issue , 2000, Pages 181-204

High-speed VLSI arithmetic units: Adders and multipliers

Author keywords

Adders; Algorithm design and analysis; Delay; Logic gates; Multiplexing; Transistors; Very large scale integration

Indexed keywords

LOGIC GATES; MULTIPLEXING; TRANSISTORS; VLSI CIRCUITS;

EID: 84894279293     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1109/9780470544365.ch10     Document Type: Chapter
Times cited : (26)

References (38)
  • 1
    • 84902523472 scopus 로고
    • Digital Computer Arithmetic: A Unified Algorithmic Specification
    • Polytechnic Institute of Brooklyn, April 13-15
    • A. Avizienis, “Digital Computer Arithmetic: A Unified Algorithmic Specification,” Symposium on Computers and Automata, Polytechnic Institute of Brooklyn, April 13-15, 1971.
    • (1971) Symposium on Computers and Automata
    • Avizienis, A.1
  • 2
    • 0004205671 scopus 로고
    • IEEE Computer Society Press, Piscataway, NJ
    • Earl E. Swartzlander, Computer Arithmetic, vols. 1 and 2. Ieee Computer Society Press, Piscataway, NJ, 1990.
    • (1990) Computer Arithmetic , vol.1-2
    • Swartzlander, E.E.1
  • 6
    • 24944572091 scopus 로고
    • Parallel Addition in Digital Computers: A New Fast “Carry Circuit,”
    • September
    • T. Kilburn, D. B. G. Edwards, and D. Aspinall, “Parallel Addition in Digital Computers: A New Fast “Carry” Circuit,” Proceedings IEE, vol. 106, Pt. B. P. 464, September 1959.
    • (1959) Proceedings IEE , vol.106 , pp. 464
    • Kilburn, T.1    Edwards, D.B.G.2    Aspinall, D.3
  • 7
    • 85065824578 scopus 로고
    • Some Optimal Schemes for ALU Implementation in VLSI Technology
    • June 4-6, University of Illinois, Urbana, IL
    • V. G. Oklobdzija and E. R. Barnes, “Some Optimal Schemes for ALU Implementation in VLSI Technology,” Proceedings of 7th Symposium on Computer Arithmetic, June 4-6, 1985, University of Illinois, Urbana, IL.
    • (1985) Proceedings of 7Th Symposium on Computer Arithmetic
    • Oklobdzija, V.G.1    Barnes, E.R.2
  • 10
    • 0025419522 scopus 로고
    • A 3.8 ns CMOS 16 x 16-b Multiplier Using Complementary PassTransistor Logic
    • K. Yano, et al., “A 3.8 ns CMOS 16 x 16-b Multiplier Using Complementary PassTransistor Logic,” IEEE Journal of Solid-State Circuits, vol. 25, pp. 388-395, April 1990.
    • (1990) IEEE Journal of Solid-State Circuits , vol.25 , pp. 388-395
    • Yano, K.1
  • 12
    • 0028099002 scopus 로고
    • A 4.4-ns CMOS 54 x 54-b Multiplier Using Pass-transistor Multiplexer
    • San Diego, CA, May 1-4
    • N. Ohkubo, et al., “A 4.4-ns CMOS 54 x 54-b Multiplier Using Pass-transistor Multiplexer,” Proceedings of the Custom Integrated Circuits Conference, San Diego, CA, May 1-4, 1994.
    • (1994) Proceedings of the Custom Integrated Circuits Conference
    • Ohkubo, N.1
  • 16
    • 0015651305 scopus 로고
    • A Parallel Algorithms for the Efficient Solution of a General Class of Recurrence Equations
    • Aug
    • P. M. Kogge and H. S. Stone, “A Parallel Algorithms for the Efficient Solution of a General Class of Recurrence Equations,” IEEE Transactions on Computers, vol. C-22, no. 8, Aug. 1973, pp. 786-793.
    • (1973) IEEE Transactions on Computers , vol.C-22 , Issue.8 , pp. 786-793
    • Kogge, P.M.1    Stone, H.S.2
  • 18
    • 0020102009 scopus 로고
    • A Regular Layout for Parallel Adders
    • March
    • R. P. Brent and H. T. Kung, “A Regular Layout for Parallel Adders,” IEEE Transactions on Computers, vol. C-31, no. 3, March 1982, pp. 260-264.
    • (1982) IEEE Transactions on Computer , vol.C-31 , Issue.3 , pp. 260-264
    • Brent, R.P.1    Kung, H.T.2
  • 20
    • 0030086663 scopus 로고    scopus 로고
    • A Sub-Nanosecond 0.5 μm 64 b Adder Design
    • Digest of Technical Papers, San Francisco, February
    • S. Naffziger, “A Sub-Nanosecond 0.5 μm 64 b Adder Design,” 1996 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, San Francisco, February 810, 1996, pp. 362-363.
    • (1996) 1996 IEEE International Solid-State Circuits Conference , vol.810 , pp. 362-363
    • Naffziger, S.1
  • 23
    • 0026955423 scopus 로고
    • A 200 MHz 64-b Dual-Issue CMOS Microprocessor
    • Nov
    • D. Dobberpuhl, et al., “A 200 MHz 64-b Dual-Issue CMOS Microprocessor,” IEEE Journal of Solid-State Circuits, vol. 27, no. 11, Nov. 1992.
    • (1992) IEEE Journal of Solid-State Circuits , vol.27 , Issue.11
    • Dobberpuhl, D.1
  • 24
    • 0015049733 scopus 로고
    • A 40 ns 17-bit array multiplier
    • April
    • S. D. Pezaris, “A 40 ns 17-bit array multiplier,” IEEE Transactions on Computers, vol. C-20, pp. 442-447, April 1971.
    • (1971) IEEE Transactions on Computers , vol.C-20 , pp. 442-447
    • Pezaris, S.D.1
  • 26
    • 0001342967 scopus 로고
    • Some Schemes for Parallel Multipliers
    • March
    • L. Dadda, “Some Schemes for Parallel Multipliers,” Alta Frequenza, vol. 34, pp. 349-356, March 1965.
    • (1965) Alta Frequenza , vol.34 , pp. 349-356
    • Dadda, L.1
  • 27
    • 0017542921 scopus 로고
    • A Compact High Speed Parallel Multiplication Scheme
    • Feb
    • W. J. Stenzel, “A Compact High Speed Parallel Multiplication Scheme,” IEEE Transaction on Computers, vol. C-26, pp. 948-957, Feb. 1977.
    • (1977) IEEE Transaction on Computers , vol.C-26 , pp. 948-957
    • Stenzel, W.J.1
  • 29
    • 0027615316 scopus 로고
    • M x N Booth Encoded Multiplier Generator Using Optimized Wallace Trees
    • June
    • J. Fadavi-Ardekani, “M x N Booth Encoded Multiplier Generator Using Optimized Wallace Trees,” IEEE Transactions on VLSI Systems, vol. 1, no. 2, June 1993.
    • (1993) IEEE Transactions on VLSI Systems , vol.1 , Issue.2
    • Fadavi-Ardekani, J.1
  • 30
    • 17644373718 scopus 로고    scopus 로고
    • A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach
    • March
    • V. G. Oklobdzija, D. Villeger, and S. S. Liu, “A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach,” IEEE Transaction on Computers, vol. 45, no. 3, March 1996.
    • (1996) IEEE Transaction on Computers , vol.45 , Issue.3
    • Oklobdzija, V.G.1    Villeger, D.2    Liu, S.S.3
  • 31
    • 0001146101 scopus 로고
    • A Signed Binary Multiplication Technique
    • A. D. Booth, “A Signed Binary Multiplication Technique,” Quarterly J. Meehan. Appl. Math., vol. Iv, 1951.
    • (1951) Quarterly J. Meehan. Appl. Math , vol.4
    • Booth, A.D.1
  • 32
    • 84937349985 scopus 로고
    • High Speed Arithmetic in Binary Computers
    • Jan
    • O. L. Macsorley, “High Speed Arithmetic in Binary Computers,” Proceedings of IRE, vol. 49, no. 1, Jan. 1961.
    • (1961) Proceedings of IRE , vol.49 , Issue.1
    • Macsorley, O.L.1
  • 34
    • 0031273026 scopus 로고    scopus 로고
    • A 4.1 nS Compact 54 x 54-b Multiplier Utilizing Sign-Select Booth Encoders
    • Nov
    • G. Goto, et al., “A 4.1 nS Compact 54 x 54-b Multiplier Utilizing Sign-Select Booth Encoders,” IEEE Journal of Solid-State Circuits, vol. 32, no. 11, Nov. 1997, pp. 1676-1682.
    • (1997) IEEE Journal of Solid-State Circuits , vol.32 , Issue.11 , pp. 1676-1682
    • Goto, G.1
  • 36
    • 85036624861 scopus 로고    scopus 로고
    • A 15nS 32 x 32-bit CMOS Multiplier with an Improved Parallel Structure
    • Digest of technical papers
    • M. Nagamatsu, et al., “A 15nS 32 x 32-bit CMOS Multiplier with an Improved Parallel Structure,” IEEE Custom Integrated Circuits Conference 1989. Digest of technical papers.
    • IEEE Custom Integrated Circuits Conference 1989
    • Nagamatsu, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.