On the generation and recovery of hot carrier induced interface traps: A critical examination of the 2-D R-D model

IEEE Electron Device Letters

Volumn 27, Issue 3, 2006, Pages 188-190

  Saha, D ^a   Varghese, D ^a   Mahapatra, Souvik ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

Author keywords

Charge pumping; Hot carrier injection; Interface traps; Reaction diffusion model

Indexed keywords

CHEMICAL BONDS; ELECTRON TRAPS; HOT CARRIERS; MATHEMATICAL MODELS; OXYGEN; SILICON;

CHARGE PUMPING; HOT CARRIER INJECTION STRESS; INTERFACE TRAPS; REACTION DIFFUSION MODEL;

ELECTRON DEVICES;

EID: 33644630332     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2006.870241     Document Type: Article

References (17)

1. P. Heremans, R. Bellens, G. Groeseneken, and H. E. Maes, "Consistent model for the hot carrier degradation in n-channel and p-channel MOSFETs," IEEE Trans. Electron Devices, vol. 35, no. 12, pp. 2194-2209, Dec. 1988.
2. 2 interface," Appl. Phys. Lett., vol. 61, no. 7, pp. 807-809, 1992.
3. G. Groeseneken, R. Bellens, G. V. Den Bosch, and H. E. Maes, "Hot carrier degradation in submicrometer MOSFETs: From uniform injection toward the real operating conditions," Semicond. Sc. Technol., vol. 10, p. 1028, 1995.
4. S. Mahapatra, C. D. Parikh, V. R. Rao, C. R. Viswanathan, and J Vasi, "Device scaling effects on hot-carrier induced interface and oxide trapped charge distributions in MOSFETs," IEEE Trans. Electron Devices, vol. 47, no. 4, pp. 789-796, Apr. 2000.
5. J.-H. Shiue, J. Y. Lee, and T.-S. Chao, "A study of interface trap generation by Fowler-Nordheim and substrate-hot-carrier stresses for 4-nm thick gate oxides," IEEE Trans. Electron Devices, vol. 46, no. 8, pp. 1705-1710, Aug. 1999.
6. K. Uwasawa, T. Yamamoto, and T. Mogami, "A new degradation mode of scaled p+ polysilicon gate p-MOSFETs induced by bias temperature instability," in IEDM Tech Dig., 1995, pp. 871-874.
7. T. Yamamoto, K. Uwasawa, and T. Mogami, "Bias temperature instability in scaled p+ polysilicon gate p-MOSFETs," IEEE Trans. Electron Devices, vol. 46, no. 5, pp. 921-926, May 1999.
8. S. Mahapatra, P. B. Kumar, and M. A. Alam, "Investigation and modeling of interface and bulk trap generation during negative bias temperature instability in p-MOSFETs," IEEE Trans. Electron Devices, vol. 51, no. 9, pp. 1371-1379, Sep. 2004.
9. K. O. Jeppson and C. M. Svensson, "Negative bias stress of MOS devices at high electric fields and degradation of MOS devices," J. Appl. Phys., vol. 48, pp. 2004-2014, 1977.
10. M. A. Alam, "A critical examination of the mechanics of dynamic NBTI for p-MOSFETs," in IEDM Tech. Dig., 2003, pp. 345-348.
11. S. Chakravarthi, A. T. Krishnan, V. Reddy, C. F. Machala, and S. Krishnan, "A comprehensive framework for predictive modeling of negative bias temperature instability," in Proc. Int. Reliability Physics Symp., 2004, pp. 273-282.
12. H. Kufluoglu and M. A. Alam, "A geometrical unification of the theories of NBTI and HCI time exponents and its implications for ultra-scaled planer and surround gate MOSFETs," in IEDM Tech. Dig., 2004, pp. 113-116.
13. 2 interface," IEEE Electron Device Lett., vol. 26, no. 8, pp. 572-574, Aug. 2005.
14. G. Groeseneken, H. E. Maes, N. Beltran, and R. F. D. Keersmaecker, "A reliable approach to charge pumping measurements inMOS transistors," IEEE Trans. Electron Devices, vol. ED-31, no. 1, pp. 42-53, Jan. 1984.
15. S. Rangan, N. Mielke, and E. C. C. Yeh, "Universal recovery behavior of negative bias temperature instability," in IEDM Tech. Dig., 2003, pp. 341-344.
16. "Users Manual," ISE TCAD.
17. J. D. Bude, M. R. Pinto, and R. K. Smith, "Monte Carlo simulation of CHISEL flash memory cell," IEEE Trans. Electron Devices, vol. 47, no. 10, pp. 1873-1881, Oct. 2000.