Low-power high-performance double-gate fully depleted SOI circuit design

IEEE Transactions on Electron Devices

Volumn 49, Issue 5, 2002, Pages 852-862

  Zhang, Rongtian ^b   Roy, Kaushik ^a,b  

^a IEEE

^b PURDUE UNIVERSITY   (United States)

Author keywords

Circuit design; CMOS; Double gate fully depleted SOI; High performance; Low power

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POWER SUPPLIES TO APPARATUS; LEAKAGE CURRENTS; MOSFET DEVICES; RELIABILITY; SEMICONDUCTING FILMS; SEMICONDUCTING SILICON; SILICON ON INSULATOR TECHNOLOGY; VLSI CIRCUITS;

BACKCHANNEL LEAKAGE; DOUBLE-GATE FULLY DEPLETED CIRCUIT; SHORT CHANNEL EFFECT; SILICON ON INSULATOR CIRCUIT DESIGN; SOFTWARE PACKAGE MEDICI;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036563982     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.998595     Document Type: Article

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