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Volumn 26, Issue 3, 2003, Pages 56-60

The 1 billion transistor processor: Who will be first?

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; DIFFRACTION; DIFFUSION; FUNCTIONS; GRAPHIC METHODS; INTEGRATION; OPTICAL INTERCONNECTS; OPTIMIZATION; PHOTOLITHOGRAPHY; PROBLEM SOLVING; PROGRAM PROCESSORS; RESEARCH AND DEVELOPMENT MANAGEMENT; SEMICONDUCTOR JUNCTIONS; THERMODYNAMIC STABILITY;

EID: 3142585603     PISSN: 01633767     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Review
Times cited : (5)

References (19)
  • 3
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    • Intel describes billion-transistor four core itanium processor
    • Oct. 16
    • Anthony Cataldo, "Intel Describes Billion-Transistor Four Core Itanium Processor," EE Times, Oct. 16, 2002.
    • (2002) EE Times
    • Cataldo, A.1
  • 4
    • 0034785113 scopus 로고    scopus 로고
    • 2 gate dielectrics with dual poly-Si gate electrodes
    • 2 Gate Dielectrics with Dual Poly-Si Gate Electrodes," VLSI Technology Symposium Digest, 2001, p. 133.
    • (2001) VLSI Technology Symposium Digest , pp. 133
    • Lee, S.J.1
  • 7
    • 0036867765 scopus 로고    scopus 로고
    • Electrical properties of 1.5 nm SiON gate dielectric using radical oxygen and radical nitrogen
    • November
    • M. Togo et al., "Electrical Properties of 1.5 nm SiON Gate Dielectric Using Radical Oxygen and Radical Nitrogen," IEEE Transaction on Electron Devices, November 2002, p. 1903.
    • (2002) IEEE Transaction on Electron Devices , pp. 1903
    • Togo, M.1
  • 9
    • 0036867745 scopus 로고    scopus 로고
    • Damascene W/TiN gate MOSFET with improved performance for 0.1 μm regime
    • Nov.
    • R. Li et al., "Damascene W/TiN Gate MOSFET with Improved Performance for 0.1 μm Regime," IEEE Transactions on Electron Devices, Nov. 2002.
    • (2002) IEEE Transactions on Electron Devices
    • Li, R.1
  • 10
    • 0035717522 scopus 로고    scopus 로고
    • 2) polysilicon: A novel approach to very low resistive gate (20hm/sq) without metal CMP nor etching
    • 2) Polysilicon: A Novel Approach to Very Low Resistive Gate (20hm/sq) Without Metal CMP nor Etching," IEDM Technical Digest, 2001, p. 825.
    • (2001) IEDM Technical Digest , pp. 825
    • Travel, B.1
  • 12
    • 0036507826 scopus 로고    scopus 로고
    • Maintaining the benefits of CMOS scaling when scaling bogs down
    • E.J. Nowak, "Maintaining the Benefits of CMOS Scaling When Scaling Bogs Down," IBM Journal of Research and Development, Vol. 26, No. 2/3, 2002.
    • (2002) IBM Journal of Research and Development , vol.26 , Issue.2-3
    • Nowak, E.J.1
  • 15
    • 0034453893 scopus 로고    scopus 로고
    • Current and future low-k dielectrics for Cu interconnects
    • T. Kikkawa, "Current and Future Low-k Dielectrics for Cu Interconnects," IEDM Technical Digest, 2000, p. 253.
    • (2000) IEDM Technical Digest , pp. 253
    • Kikkawa, T.1
  • 16
    • 18344401509 scopus 로고    scopus 로고
    • A 50 nm depleted substrate CMOS transistor (DST)
    • R. Chau et al., "A 50 nm Depleted Substrate CMOS Transistor (DST)," IEDM Technical Digest, 2001, p. 621.
    • (2001) IEDM Technical Digest , pp. 621
    • Chau, R.1
  • 17
    • 0035717948 scopus 로고    scopus 로고
    • Sub-20 nm CMOS FinFET technologies
    • Y. Choi et al., "Sub-20 nm CMOS FinFET Technologies," IEDM Technical Digest, 2001, p. 421.
    • (2001) IEDM Technical Digest , pp. 421
    • Choi, Y.1
  • 18
    • 0035714368 scopus 로고    scopus 로고
    • Triple self-aligned, planar double-gate MOSFETs: Devices and circuits
    • K.W. Guarini et al., "Triple Self-Aligned, Planar Double-Gate MOSFETs: Devices and Circuits," IEDM Technical Digest, 2001, p. 425.
    • (2001) IEDM Technical Digest , pp. 425
    • Guarini, K.W.1
  • 19
    • 0037646045 scopus 로고    scopus 로고
    • Advanced depleted-substrate transistors: Single-gate, double-gate, and tri-gate
    • Sept. 17-19, Nagoya, Japan
    • R. Chau et al., "Advanced Depleted-Substrate Transistors: Single-Gate, Double-Gate, and Tri-Gate," International Solid State Devices and Materials Conference, Sept. 17-19, 2002, Nagoya, Japan, www.intel.com/ research/silicon.
    • (2002) International Solid State Devices and Materials Conference
    • Chau, R.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.