Variable partitioning for dual memory bank DSPs

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn 2, Issue , 2001, Pages 1121-1124

  Leupers, R ^a   Kotte, D ^a  

^a TU DORTMUND UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDWIDTH; C (PROGRAMMING LANGUAGE); DATA STORAGE EQUIPMENT; PROGRAM COMPILERS; RESPONSE TIME (COMPUTER SYSTEMS);

MEMORY BANKS; TIME CRITICAL ALGORITHMS; VARIABLE PARTITIONING;

DIGITAL SIGNAL PROCESSING;

EID: 0034854710     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. DSPStone - A DSP-oriented benchmarking methodology
2. TI C62x performance code optimization
3. Direct synthesis of optimized DSP assembly code from signal flow block diagrams
4. Exploiting dual data-memory banks in digital signal processors
5. Simultaneous reference allocation in code generation for dual data memory bank ASIPs
6. Gepard - A parameterisable DSP core for ASICs
7. Some experiments in local microcode compaction for horizontal machines