Integrated scheduling and register assignment for VLIW-DSP architectures

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 2001, Pages 339-343

  Zeitlhofer, T ^a   Wess, B ^a  

^a VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL SIGNAL PROCESSING; ENCODING (SYMBOLS); OPTIMIZATION; RESOURCE ALLOCATION; VERY LONG INSTRUCTION WORD ARCHITECTURE; VIRTUAL REALITY;

HETEROGENEOUS FUNCTIONAL UNITS; HETEROGENEOUS REGISTER SETS; INTEGRATED REGISTER ASSIGNMENT; INTEGRATED SCHEDULING ASSIGNMENT; VIRTUAL RESOURCES;

INTEGRATING CIRCUITS;

EID: 0034776269     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. HARE: A hierarchical allocator for registers in multiple issue architectures
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6. Register allocation by priority-based coloring
7. Local microcode compaction techniques
8. Register allocation with instruction scheduling: A new approach
9. Flexible issue slot assignment for VLIW architectures
10. Constraint analysis for code generation: Basic techniques and applications in FACTS
11. Operation scheduling for parallel functional units using genetic algorithms