Architectures and design techniques for energy efficient embedded DSP and multimedia processing

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 2, Issue , 2004, Pages 988-993

  Verbauwhede, Ingrid ^a,b   Schaumont, Patrick ^a   Piguet, Christian ^c   Kienhuis, Bart ^d  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c CSEM   (Switzerland)

^d NONE

Author keywords

[No Author keywords available]

Indexed keywords

SYSTEM-ON-CHIP (SOC); VIDEO DECODING; VITERBI DECODING; DESIGN AND INTEGRATIONS; HETEROGENEOUS ARCHITECTURES; HETEROGENEOUS COLLECTIONS; LEVEL OF ABSTRACTION; MULTIMEDIA PROCESSING; MULTIPLE FUNCTION; PROGRAMMING ENVIRONMENT; SYSTEMS ON CHIPS;

ALGORITHMS; DATA PROCESSING; DIGITAL SIGNAL PROCESSING; GLOBAL POSITIONING SYSTEM; MICROCONTROLLERS; MICROPROCESSOR CHIPS; MULTIMEDIA SYSTEMS; VIDEODISKS; EMBEDDED SYSTEMS; ENERGY EFFICIENCY; EXHIBITIONS;

EMBEDDED SYSTEMS; DESIGN;

EID: 3042653170     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1269022     Document Type: Conference Paper

References (19)

1. D. Ching, P. Schaumont, I. Verbauwhede, "Integrated Modeling and Generation of a Reconfigurable Network-On-Chip," UCLA IVgroup Technical Report, September 2003.
2. W. Dally, B. Towles, "Route Packets, not wires: on-chip interconnection networks," Proc. DAC 2001.
3. R. David et al. « Low-Power Reconfigurable Processors", Chapter 20 in "Low Power Electronics Design", edited by C. Piguet, CRC Press, will be published in April 2004.
4. GEZEL kernel, http://www.ee.ucla.edu/~schaum/gezel
5. B. Kienhuis, et al."A Methodology to Design Programmable Embedded Systems", LNCS, Vol 2268, Nov. 2001.
6. J. Kim, et al., "A 2-Gb/s/pin Source Synchronous CDMA Bus Interface with simultaneous Multi-Chip Access and Reconfigurable I/O capability", CICC, Sept 2003.
7. MPICH - A portable implementation of MPI, http://www-unix.mcs.anl.gov/ mpi/mpich/
8. P. Mosch et al. « A 720 μW 50 MOPS IV. DSP for a Hearing Aid Chip Set", Proc. ISSCC, pp. 238-239, Feb. 2000.
9. zg n Paker et al. "A heterogeneous multi-core platform for low power signal processing in systems-on-chip", ESSCIRC 2002.
10. W. Qin, S. Malik, "Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation," Proceedings of DATE 2003, Mar, 2003, pp.556-561.
11. F. Rarnpogna et al. « Magic, a Low-Power, re-configurable DSP", Chapter 21 in "Low Power Electronics Design", ed. C. Piguet, CRC Press, published in April 2004.
12. P. Schaumont, I. Verbauwhede, M. Sarrafzadeh, K. Keutzer, "A quick safari through the reconfiguration jungle," Proceedings DAC 2001,pg. 172-177, June 2001.
13. T. Stefanov, C. Zissulescu, A. Turjan, B. Kienhuis, E. Deprettere,"System Design using Kahn Process Networks: The Compaan/Laura Approach", DATE2004, Feb 2004, Paris, France.
14. T. Stefanov, B. Kienhuis, E. Deprettere, "Algorithmic Transformation Techniques for Efficient Exploration of Alternative Application Instances", Proc. CODES'2002, Colorado, May 2002.
15. I. Verbauwhede, J. M. Rabaey. "Synthesis of Real-Time Systems: Solutions and challenges" Journal of VLSI Signal Processing, Vol. 9, No. 1/2, Jan. 1995, pp. 67-88.
16. I. Verbauwhede, M.C. F. Chang, "Reconfigurable Interconnect for next generation systems", Proc. SLIP, pp. 71-74, April 2002.
17. Xilmx: Virtex-II-Pro Platform FPGAs: Introduction and Overview and Functional Description, Aug. 2003, Oct. 2003, www.xilinx.com/bvdocs/ publications/ds083-1.pdf, ds083-2.pdf.
18. H. Zhang, et al., "A 1V Heterogeneous Reconfigurable Processor IC for Baseband Wireless Applications," IEEE Journal on Solid State Circuits, November 2000.
19. C. Zissulescu, et al., "Laura: Leiden Architecture Research and Exploration Tool", Proc. FPL 2003.