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Volumn , Issue , 2004, Pages 58-63

Application of a multi-processor SoC platform to high-speed packet forwarding

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED PROCESSORS; HIGH SPEED PACKET FORWARDING; INTERNET PROTOCOL (IP); INTERPROCESSOR COMMUNICATION;

EID: 3042651236     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1269203     Document Type: Conference Paper
Times cited : (17)

References (24)
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  • 7
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    • A heterogeneous multiprocessor architecture for flexible media processing
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    • M. Rutten et al., "A Heterogeneous Multiprocessor Architecture for Flexible Media Processing", IEEE Design & Test of Computers, 19(4):39-50, July 2002.
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    • Rutten, M.1
  • 8
    • 0035444259 scopus 로고    scopus 로고
    • Viper: A multiprocessor SoC for advanced set-top box and digital TV systems
    • September
    • S. Dutta et al., "Viper: A Multiprocessor SoC for Advanced Set-Top Box and Digital TV Systems", IEEE Design & Test of Computers, 18(5):21-31, September 2001.
    • (2001) IEEE Design & Test of Computers , vol.18 , Issue.5 , pp. 21-31
    • Dutta, S.1
  • 10
    • 3042666142 scopus 로고    scopus 로고
    • The mescal architecture development system (tipi) tutorial
    • UCB/ERLM03/40, Electronics Research Lab, University of California at Berkeley, October
    • M. Gries, S. Weber and C. Brooks, "The Mescal Architecture Development System (tipi) Tutorial", Technical Report, UCB/ERLM03/40, Electronics Research Lab, University of California at Berkeley, October 2003.
    • (2003) Technical Report
    • Gries, M.1    Weber, S.2    Brooks, C.3
  • 13
    • 0036857007 scopus 로고    scopus 로고
    • StepNP: A system-level exploration platform for network processors
    • Nov.
    • P. G. Paulin, C. Pilkington, E. Bensoudane, "StepNP: A System-Level Exploration Platform for Network Processors", IEEE Design & Test of Computers, vol. 19, no.6, Nov. 2002, pp. 17-26.
    • (2002) IEEE Design & Test of Computers , vol.19 , Issue.6 , pp. 17-26
    • Paulin, P.G.1    Pilkington, C.2    Bensoudane, E.3
  • 15
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    • A system-level exploration platform and methodology for network applications based on configurable processors
    • Paris, Feb.
    • D. Quinn et al, "A System-level Exploration Platform and Methodology for Network Applications Based on Configurable Processors", Proc. of Design Automation and Test in Europe (DATE), Paris, Feb. 2004.
    • (2004) Proc. of Design Automation and Test in Europe (DATE)
    • Quinn, D.1
  • 17
    • 3042585108 scopus 로고    scopus 로고
    • See ST web site: http://www.stmcu.com/inchtml-pages-STBus_intro.html
    • ST Web Site
  • 19
    • 0038645161 scopus 로고    scopus 로고
    • An 800MHz star-connected on-chip network for application to systems on a chip
    • San Francisco, Feb.
    • S.-J. Lee et al, "An 800MHz Star-Connected On-Chip Network for Application to Systems on a Chip", Proc. of Intl. Solid-State Circuits Conference (ISSC), San Francisco, Feb. 2003.
    • (2003) Proc. of Intl. Solid-state Circuits Conference (ISSC)
    • Lee, S.-J.1
  • 20
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    • San Francisco, Feb.
    • M. Borgatti et al, "A 0.1 Sum, 1GOPS Reconfigurable Signal Processing IC with embedded FPGA and 1.2GB/S, 3-Port Flash Memory Subsystem", Proc. of Intl. Solid-State Circuits Conference (ISSC), San Francisco, Feb. 2003.
    • (2003) Proc. of Intl. Solid-state Circuits Conference (ISSC)
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  • 22
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    • A multi-processor SoC platform and tools for communications applications
    • CRC Press, to appear in May
    • P. G. Paulin, C. Pilkington, E. Bensoudane, M. Langevin, "A Multi-Processor SoC Platform and Tools for Communications Applications", in Embedded Systems Handbook, CRC Press, to appear in May 2004.
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  • 23
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.