Access pattern based local memory customization for low power embedded systems

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2001, Pages 778-784

  Grun, Peter ^a   Dutt, Nikil ^a   Nicolau, Alex ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS PATTERNS; BANDWIDTH REQUIREMENT; CACHE CONFIGURATIONS; LOCALITY TYPES; LOW POWER EMBEDDED SYSTEMS; MEMORY ACCESS; POWER REDUCTIONS; REAL-LIFE APPLICATIONS;

BANDWIDTH; EMBEDDED SYSTEMS; EXHIBITIONS; MEMORY ARCHITECTURE;

CACHE MEMORY;

EID: 3042601599     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2001.915120     Document Type: Conference Paper

References (31)

1. L. Benini, A. Macii, E. Macii, M. Poncino, and R. Scarsi. Architectures and synthesis algorithms for power-efficient bus interfaces. TCAD, 19(9), 2000.
2. D. Brooks, V. Tiwary, and M. Martonosi. Wattch: A framework for architectural-level power analysis and optimizations. In ISCA, 2000.
3. D. Callahan, K. Kennedy, and A. Porterfield. Software prefetching. In ASPLOS, 1991.
4. F. Catthoor, S. Wuytack, E. De Greef, F. Balasa, L. Nachtergaele, and A. Vandecappelle. Custom Memory Management Methodology. Kluwer, 1998.
5. T-F. Chen and J-L. Baer. A performance study of software and hardware data prefetching schemes. In ISCA, 1994.
6. K. Diefendorff and P. Dubey. How multimedia workloads will change processor design. In Micro, 1997.
7. S. Rixner et. al. Memory access scheduling. In ISCA, 2000.
8. A. Gonzales, C. Aliagas, and M. Valero. A data cache with multiple caching strategies tuned to different types of locality. In International Conference on Supercomputing (ICS), 1995.
9. P. Grun, N. Dutt, and A. Nicolau. Early local memory exploration for low power. Technical report, University of California, Irvine, 2000.
10. P. Grun, N. Dutt, and A. Nicolau. Memory aware compilation through accurate timing extraction. In DAC, 2000.
11. P. Grun, N. Dutt, and A. Nicolau. Mist: An algorithm for memory miss traffic management. In To Appear in ICCAD, San Jose, 2000.
12. P. Grun, A. Halambi, N. Dutt, and A. Nicolau. RTGEN: An algorithm for automatic generation of reservation tables from architectural descriptions. In ISSS, 1999.
13. A. Halambi, P. Grun, V. Ganesh, A. Khare, N. Dutt, and A. Nicolau. EXPRESSION: A language for architecture exploration through compiler/simulator retargetability. In Proc. DATE, March 1999.
14. A. Huang and J. Shen. A limit study of local memory requirements using value reuse profile. In Annual Symposium of Microarchitecture, 1995.
15. IBM Microelectronics, Data Sheets for Synchronous DRAM IBM0316409C. www.chips. ibm. com/products/memory/08J3348/.
16. A. Khare, N. Savoiu, A. Halambi, P. Grun, N. Dutt, and A. Nicolau. V-SAT: A visual specification and analysis tool for system-on-chip exploration. In Proc. EUROMICRO, October 1999.
17. C. Kulkami, F. Catthoor, and H. De Man. Code transformations for low power caching in embedded multimedia processors. In Intnl. Parallel Processing Symposium (IPPS), Orlando, FL, 1998.
18. D. Lee, P. Crowley, J-L. Baer, T. Anderson, and B. Bershad. Execution characteristics of desktop applications on windows nt. In ISCA, 1998.
19. C. Luk and T. Mowry. Memory forwarding: Enabling aggressive layout optimizations by guaranteeing the safety of data relocation. In ISCA, 1999.
20. P. Mishra, P. Grun, N. Dutt, and A. Nicolau. Processor-memory co-explotation driven by a memory-aware architecture description language. In To Appear in International Conference on VLSI Design, Bangalore, India, 2001.
21. S. Palacharla and R. Kessler. Evaluating stream buffers as a secondary cache replacement. In ISCA, 1994.
22. P. Panda, N. Dutt, and N. Nicolau. Memory Issues in Embedded Systems-on-Chip. Kluwer, 1999.
23. P. R. Panda, N. D. Dutt, and A. Nicolau. Low power memory mapping through reducing address bus activity. In IEEE Transactions on VLSI.
24. Betty Prince. High Performance Memories, New Architecture DRAMs and SRAMs evolution and function. Wiley, West Sussex, 1996.
25. S. Przybylski. Sorting out the new DRAMs. In Hot Chips Tutorial, Stanford, CA, 1997.
26. P. Ranganathan, S. Adve, and N. Jouppi. Performance of image and video processing with general-purpose processors and media isa extensions. In ISCA, 1999.
27. P. Ranganathan, S. Adve, and N. Jouppi. Reconfigurablecaches and their application to media processing. In ISCA, 2000.
28. Sun Microsystems, The Shade Simulator, sw.sun. com/shade.
29. A. Veidenbaum, W. Tang, R. Gupta, A. Nicolau, and X. Ji. Adapting cache line size to application behavior. In ICS, 1999.
30. M. Wolf and M. Lam. A data locality optimizing algorithm. In PLDI, 1991.
31. S. Wuytack, F. Catthoor, G. De Jong, B. Lin, and H. De Man. Flow graph balancing for minimizing the required memory bandwith. In ISSS, La Jolla, CA, 1996.