V-SAT: A visual specification and analysis tool for system-on-chip exploration

Conference Proceedings of the EUROMICRO

Volumn 1, Issue , 1999, Pages 196-203

  Khare, Asheesh ^a   Savoiu, Nicolae ^a   Halambi, Ashok ^a   Grun, Peter ^a   Dutt, Nikil ^a   Nicolau, Alex ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CO-DESIGN FLOW; DESIGN SPACE EXPLORATION; DETAILED DESIGN; PIPELINE STRUCTURE; SOC ARCHITECTURE; SYSTEM ON CHIPS; SYSTEM-ON-CHIP ARCHITECTURE; VISUAL SPECIFICATION;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; INFORMATION SCIENCE; PROGRAMMABLE LOGIC CONTROLLERS; SPECIFICATIONS; TOOLS;

COMPUTER ARCHITECTURE;

EID: 84889020464     PISSN: 10896503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EURMIC.1999.794466     Document Type: Conference Paper

References (17)

1. G. Hadjiyiannis et al. ISDL: An instruction set description language for retargetability. In Proc. DAC, 1997.
2. P. Paulin et al. FlexWare: A flexible firmware development environment for embedded systems. In Proc. Dagstuhl Code Generation Workshop, 1994.
3. V. Zivojnovic et al. LISA-machine description language and generic machine model for HW/SW co-design. In IEEE Workshop on VLSI Signal Processing, 1996.
4. M. Freericks. The nML machine description formalism. Technical Report TR SM-IMP/DIST/08, TU Berlin CS Dept., 1993.
5. A. Halambi, P. Grun, V. Ganesh, A. Khare, N. Dutt, and A. Nicolau. EXPRESSION: A language for architecture exploration through compiler/simulator retargetability. In Proc. DATE, March 1999.
6. J. L. Hennessy and D. A. Patterson. Computer Architecture: A Quantitative Approach. Morgan Kaufmann Publishers, Inc., San Francisco, 1996.
7. Improv Incorporated. http://www.improvsys.com.
8. D. Keitel-Schulz and N. Wehn. Issues in embedded DRAM development and applications. In Proc. ISSS, December 1998.
9. A. Khare, N. Savoiu, A. Halambi, P. Grun, N. Dutt, and A. Nicolau. V-SAT: A visual specification and analysis tool for systemon-chip exploration. Technical report, University of California, Irvine, 1999.
10. R. Leupers and P.Marwedel. Retargetable code generation based on structural processor descriptions. DAES, 3(1), 1998.
11. V. Rajesh and Rajat Moona. Processor modeling for hardware software codesign. In Proc. Int. Conf. VLSI Design, January 1999.
12. N. Ramsey andM. Fernandez. Specifying representations of machine instructions. In Proc. ACM TOPLAS,May 1997.
13. Semiconductor Industry Association. National technology roadmap for semiconductors: Technology needs, 1998.
14. C. Siska. A processor description language supporting retargetable multi-pipeline dsp program development tools. In Proc. ISSS, December 1998.
15. S. Sutarwala, P. G. Paulin, and Y. Kumar. Insulin: An instruction set simulation environment. In Proc. CHDL, April 1993.
16. Tensilica Incorporated. http://www.tensilica.com.
17. Trimaran Release: http://www.trimaran.org. The MDES User Manual, 1997.