The role of return value prediction in exploiting speculative method-level parallelism

Journal of Instruction-Level Parallelism

Volumn 5, Issue , 2003, Pages

  Hu, Shiwen ^a   Bhargava, Ravi ^a   John, Lizy Kurian ^a  

^a The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LAST VALUE PREDICTORS (LVP); STRIDE VALUE PREDICTORS (SVP); VALUR PREDICTION;

COMPUTER SIMULATION; JAVA PROGRAMMING LANGUAGE; MATHEMATICAL MODELS; OBJECT ORIENTED PROGRAMMING; PROGRAM COMPILERS;

MICROPROCESSOR CHIPS;

EID: 2942715361     PISSN: None     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper

References (30)

1. H. Akkary and M. Driscoll, "A Dynamic Multithreading Processor", in Proceedings of the 31st International Symposium on Microarchitecture, pp. 226-236, Nov. 1998.
2. M. Burtscher, A. Diwan, and M. Hauswirth, "Static Load Classification for Improving the Value Predictibility of Data-Cache Misses", in Proceeding of the ACM SIGPLAN 2002 Conference on Programming language design and implementation, pp. 222-233, June 2002.
3. B. Calder, G. Reinman, and D. Tullsen, "Selective Value Prediction", in Proceedings of the 26th International Symposium on Computer Architecture, pp. 64-74, May 1999.
4. M. Chen and K. Olukotun, "Exploiting Method-Level Parallelism in Single-Threaded Java Programs", in Proceedings of the 1998 International Conference on Parallel, Architectures and Compilation Techniques, pp. 176-184, Oct. 1998.
5. M. Cintra, and J. Torrellas, "Eliminating Squashes Through Learning Cross-Thread Violations in Speculative Parallelization for Multiprocessors", in Proceedings of the 8th International Symposium on High Performance Computer Architecture, pp. 36-47, Feb. 2002.
6. R. Cmelik and D. Keppel, "Shade: A Fast Instruction-Set Simulator for Execution Profiling", in Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and Modeling of Computer Systems, pp. 128-137, May 1994.
7. L. Codrescu and D. Wills, "Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications", IEEE Transactions on Computers, vol. 50, no. 1, pp. 67-82, Jan. 2001.
8. R. J. Eickemeyer and S. Vassiliadis, "A Load Instruction Unit for Pipelined Processors", IBM Journal of Research and Development, vol. 37, no. 4, pp. 547-564, July 1993.
9. F. Gabbay and A. Mendelson, "Speculative Execution Based on Value Prediction", Technion, Israel Institute of Technology, Technical Report 1080, 1996.
10. J. Gonzalez and A. Gonzalez. "The potential of data value speculation to boost ILP", in Proceedings of the 12th International Conference on Supercomputers, pp. 21-28, July 1998.
11. J. Gummaraju, and M. Franklin, "Branch prediction in multi-threaded processors", in Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques, pp. 179-188, Oct. 2000.
12. L. Hammond, B. A. Hubbert, M. Siu, M. K. Prabhu, M. Chen, and K. Olukotun, "The Stanford Hydra CMP", IEEE Micro, vol. 20, no. 2, pp. 71-84, Mar. 2000.
13. S. Hu, R. Bhargava and L. John, "The Role of Return Value Prediction in Exploiting Speculative Method-Level Parallelism", in Proceedings of the First Value-Prediction Workshop, June 2003.
14. V. Krishnan, J. Torrellas, "A Chip-Multiprocessor Architecture with Speculative Multithreading", IEEE Transactions on Computers, vol. 48, no. 9, pp. 866-880, Sep. 1999.
15. E. Larson, and T. Austin, "Compiler Controlled Value Prediction using Branch Predictor Based Confidence", in Proceedings of the 33rd International Symposium on Microarchitecture, pp. 327-336, Dec. 2000.
16. M. Lipasti, C. Wilkerson, and J. Shen, "Value Locality and Load Value Prediction", in Proceedings of the 7th International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 138-147, Oct. 1996.
17. M. Lipasti and J. Shen, "Exceeding the Dataflow Limit via Value Prediction", in Proceedings of the 29th Annual International Symposium on Microarchitecture, pp. 226-237, Dec. 1996.
18. P. Marcuello, J. Tubella, and A. González, "Value Prediction for Speculative Multithreaded Architectures", in Proceedings of the 32nd International Symposium on Microarchitecture, pp. 230-236, Nov. 1999.
19. J. Oplinger, D. Heine, S. Liao, B. Nayfeh, M. Lam, and K. Olukotun, "Software and Hardware for Exploiting Speculative Parallelism with a Multiprocessor", Stanford University, Computer Systems Laboratory Technical Report CSL-TR-97-715, Feb. 1997.
20. J. Oplinger, D. Heine, and M. Lam, "In Search of Speculative Thread-Level Parallelism", in Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, pp. 303-313, Oct. 1999.
21. B. Rychlik and J. P. Shen, "Characterization of Value Locality in Java Programs", in Proceedings of the 3rd IEEE Annual Workshop on Workload Characterization, pp. 12-23, Nov. 2000.
22. Y. Sazeides and J. E. Smith, "The Predictability of Data Values", in Proceedings of the 30th International Symposium on Microarchitecture, pp. 248-258, Dec. 1997.
23. Y. Sazeides and J. E. Smith, "Implementations of Context Based Value Predictors", Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Technical Report ECE97-8, Dec. 1997.
24. Y. Shuf, M. Serrano, M. Gupta, and J. Singh, "Characterizing the Memory Behavior of Java Workloads: A Structured View and Opportunities for Optimizations", in Proceedings of the ACM SIGMETRICS Conference on Measurement & Modeling Computer Systems, pp.194-205, June 2001.
25. G. Sohi, S. Breach, and T. Vijaykumar, "Multiscalar Processors", in Proceedings of the 22nd Annual International Symposium on Computer Architecture, pp. 414-425, June 1995.
26. J. G. Steffan and T. Mowry, "The Potential for Using Thread-level Data Speculation to Facilitate Automatic Parallelization", in Proceedings of 4th International Symposium on High Performance Computer Architecture, pp. 2-13, Feb. 1998.
27. K. Wang and M. Franklin. "Highly Accurate Data Value Prediction Using Hybrid Predictors", in Proceedings of the 30th International Symposium on Microarchitecture, pp. 281-290, Dec. 1997.
28. F. Warg and P. Stenstrom, "Limits on Speculative Module-level Parallelism in Imperative and Objective-oriented Programs on CMP Platforms", in Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques, pp. 221-230, Sep. 2001.
29. B. Yang, S. Moon, S. Park, J. Lee, S. Lee, J. Park, Y. C. Chung, S. Kim, K. Ebcioglu, and E. Altman, "LaTTe: A Java VM Just-in-Time Compiler with Fast and Efficient Register Allocation", in Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, pp. 128-138, Oct. 1999.
30. SPEC JVM98 Benchmarks, at http://www.spec.org/osg/jvm98.