Concurrent logic and interconnect delay estimation of MOS circuits by mixed algebraic and boolean symbolic analysis

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 2003, Pages

  Bhattacharya, Sambuddha ^a   Shi, C J Richard ^a  

^a University of Washington   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN ALGEBRA; COMPUTER SIMULATION; EQUIVALENT CIRCUITS; LOGIC CIRCUITS; MATRIX ALGEBRA; TRANSFER FUNCTIONS; VLSI CIRCUITS;

MODIFIED NODAL ANALYSIS (MNA);

MOS DEVICES;

EID: 0037743438     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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