Computing logic-stage delays using circuit simulation and symbolic elmore analysis

Proceedings - Design Automation Conference

Volumn , Issue , 2001, Pages 283-288

  McDonald, C B ^a   Bryant, R E ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; DATA REDUCTION; DELAY CIRCUITS; TRANSISTORS;

CIRCUIT SIMULATION;

LOGIC CIRCUITS;

EID: 0034855922     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/378239.378486     Document Type: Conference Paper

References (11)

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4. Boolean analysis of MOS circuits
5. Incorporating signal dependencies into static transistor-level delay calculation
6. TETA: Transistor-level engine for timing analysis
7. A systematic technique for verifying critical path delays in a 300MHz alpha CPU design using circuit simulation
8. Symbolic functional and timing verification of transistor level circuits
9. Symbolic timing simulation using cluster scheduling
10. RSIM - A logic-level timing simulator