A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications

ACM Transactions on Design Automation of Electronic Systems

Volumn 9, Issue 2, 2004, Pages 238-271

  Doboli, Alex ^a,e   Dhanwada, Nagu ^b   Nunez Aldana, Adrian ^c,f   Vemuri, Ranga ^d,g  

^a STONY BROOK UNIVERSITY   (United States)

^b IBM MICROELECTRONICS   (United States)

^c SYRACUSE UNIVERSITY   (United States)

^d UNIVERSITY OF CINCINNATI   (United States)

^e USA   (United States)

^f Syracuse University   (United States)

^g University of Cincinnati   (United States)

Author keywords

Analog synthesis; Branch and bound; Genetic algorithms; Performance estimation; VHDL AMS

Indexed keywords

ARCHITECTURE GENERATION; BRANCH-AND-BOUND; CONSTRAINT TRANSFORMATION; PERFORMANCE ESTIMATION;

ANALOG TO DIGITAL CONVERSION; BANDWIDTH; CAPACITANCE; COMPUTER AIDED DESIGN; GENETIC ALGORITHMS; INDUCTANCE; NETWORKS (CIRCUITS); SIGNAL PROCESSING;

SIGNAL TO NOISE RATIO;

EID: 2942615324     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/989995.990000     Document Type: Article

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