Heads and tails: A variable-length instruction format supporting parallel fetch and decode

CASES 2001 - Proceedings of the 2001 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

Volumn , Issue , 2001, Pages 168-175

  Pan, Heidi ^a   Asanović, Krste ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); COMPRESSION RATIO (MACHINERY); DECODING; MEMORY ARCHITECTURE; PROGRAM COMPILERS;

DIRECT EXECUTION; HIGH PERFORMANCE EMBEDDED PROCESSORS; INSTRUCTION CACHES; INSTRUCTION SET; INSTRUCTION STREAMS; MULTIPLE INSTRUCTIONS; PARALLEL INSTRUCTIONS; VARIABLE LENGTH;

EMBEDDED SYSTEMS;

EID: 43149102967     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/502217.502244     Document Type: Conference Paper

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