An FPGA design of AES encryption circuit with 128-bit keys

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2005, Pages 147-151

  Qin, Hui ^a   Sasao, Tsutomu ^a   Iguchi, Yukihiro ^b  

^a KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

^b MEIJI UNIVERSITY   (Japan)

Author keywords

AES encryption; FPGA; Pipeline

Indexed keywords

COMPUTER ARCHITECTURE; FIELD PROGRAMMABLE GATE ARRAYS; STORAGE ALLOCATION (COMPUTER); THROUGHPUT;

AES ENCRYPTION; PIPELINE; PIPELINED PARTIAL ROLLING (PPR);

CRYPTOGRAPHY;

EID: 29244468026     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1057661.1057697     Document Type: Conference Paper

References (11)

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9. http://www.altera.com
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