A universal and efficient AES co-processor for field programmable logic arrays

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3203, Issue , 2004, Pages 565-574

  Pramstaller, Norbert ^a   Wolkerstorfer, Johannes ^a  

^a GRAZ UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DATA PRIVACY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM-ON-CHIP;

ADVANCED ENCRYPTION STANDARD; CIPHER-BLOCK-CHAINING; CLOCK FREQUENCY; ENCRYPTION AND DECRYPTION; FIELD PROGRAMMABLE LOGIC; FPGA IMPLEMENTATIONS; STATE REPRESENTATION; SYSTEM ON CHIP DESIGN;

CRYPTOGRAPHY;

EID: 29244466257     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30117-2_58     Document Type: Article

References (12)

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9. S. Mangard, M. Aigner, and S. Dominikus, A Highly Regular and Scalable AES Hardware Architecture, IEEE Transactions on Computers, Vol. 52, No. 4, pp. 483-491, April 2003.
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12. Xilinx Incorporated, Silicon Solutions - Virtex Series FPGAs, http://www.xilinx.com/products/.