Efficient modular-pipelined AES implementation in counter mode on ALTERA FPGA

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2778, Issue , 2003, Pages 282-291

  Charot, François ^a   Yahya, Eslam ^b   Wagner, Charles ^a  

^a CAMPUS DE BEAULIEU   (France)

^b Information Technology Institute Giaz   (Egypt)

Author keywords

[No Author keywords available]

Indexed keywords

DATA PRIVACY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; INTEGRATED CIRCUIT DESIGN;

ADVANCED ENCRYPTION STANDARD ALGORITHMS; CONTROL SIGNAL; ENCRYPTION AND DECRYPTION; FEEDBACK MODE; FPGA IMPLEMENTATIONS; HIGH FLEXIBILITY; PROPOSED ARCHITECTURES; SINGLE-CHIP FPGA IMPLEMENTATION;

CRYPTOGRAPHY;

EID: 29244462643     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-45234-8_28     Document Type: Article

References (10)

1. Altera APEX20K, APEX 20K Devices: System-on-a-Programmable-Chip Solutions, http:/www.altera.com.
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3. M. Dworkin, Recommendation for Block Cipher Modes of Operation, NIST special Publication 800-38A, December 2001.
4. A.J. Elbirt, W. Yip, B. Chetwynd, C. Paar, An FPGA Implementation and Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists, The Third AES Candidate Conference (AES3), April 2000.
5. FIPS Publication 197, Specification for the Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, U.S. DoC/NIST, November 2001.
6. H. Kuo, I. Verbauwhe, Architectural Optimisation for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm, CHES 2001, LNCS 2162, 2001.
7. H. Lipmaa, P. Rogaway, D. Wagner, Comments to NIST concerning AES Modes of Operations CTR-Mode Encryption, Symmetric Key Block Cipher Modes of Operation Workshop, October 2000.
8. M. McLoone, J.V. McCanny, High Performance Single-Chip FPGA Rijndael Algorithm Implementations, CHES 2001, LNCS 2162.
9. M. Alam, W. Badawy, G. Jullien A Novel Pipelined Threads Architecture for AES Encryption Algorithm, ASAP 2002, July 2002.
10. Report on the Symmetric Key Block Cipher Modes of Operations Workshop. (NIST), October 2000.