메뉴 건너뛰기




Volumn 25, Issue 12, 2004, Pages 795-797

Investigation of maximum current sensing window for two-side operation, four-bit/cell MLC nitride-trapping nonvolatile flash memories

Author keywords

Four bit cell; Multilevel cells (MLCs); Nitride trapping device; NROM; Second bit effect; Two bit cell

Indexed keywords

MATHEMATICAL MODELS; MOSFET DEVICES; NONVOLATILE STORAGE; ROM; SILICON NITRIDE;

EID: 10644240078     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2004.838055     Document Type: Article
Times cited : (10)

References (8)
  • 2
    • 0001791729 scopus 로고    scopus 로고
    • "Can NROM, a two-bit trapping storage cell, give a real challenge to floating gate cells"
    • Tokyo, Japan, Sept
    • B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, " Can NROM, a two-bit trapping storage cell, give a real challenge to floating gate cells," in Proc. SSDM, Tokyo, Japan, Sept. 1999, pp. 522-524.
    • (1999) Proc. SSDM , pp. 522-524
    • Eitan, B.1    Pavan, P.2    Bloom, I.3    Aloni, E.4    Frommer, A.5    Finzi, D.6
  • 3
    • 0023313406 scopus 로고
    • "A true single-transistor oxide-nitride-oxide EEPROM device"
    • Mar
    • T. Y. Chan, K. K. Young, and C. Hu, "A true single-transistor oxide-nitride-oxide EEPROM device," IEEE Electron Device Lett., vol. EDL-8, pp. 93-95, Mar. 1987.
    • (1987) IEEE Electron. Device Lett. , vol.EDL-8 , pp. 93-95
    • Chan, T.Y.1    Young, K.K.2    Hu, C.3
  • 4
    • 31744437963 scopus 로고    scopus 로고
    • "Non-Volatile Semiconductor Memory Cell Utilizing Asymmetrical Charge Trapping"
    • June
    • B. Eitan, "Non-Volatile Semiconductor Memory Cell Utilizing Asymmetrical Charge Trapping," U.S. Patent 5 768 192, June 1998.
    • (1998) U.S. Patent 5 768 192
    • Eitan, B.1
  • 6
    • 0027239315 scopus 로고
    • "Threshold voltage modeling and the subthreshold regime of operation of short-channel MOSFETs"
    • Nov
    • T. A. Fjeldly and M. Shur, "Threshold voltage modeling and the subthreshold regime of operation of short-channel MOSFETs," IEEE Trans. Electron Devices, vol. 40, pp. 137-145, Nov. 1993.
    • (1993) IEEE Trans. Electron. Devices , vol.40 , pp. 137-145
    • Fjeldly, T.A.1    Shur, M.2
  • 7
    • 1342308176 scopus 로고    scopus 로고
    • "Modeling for the second bit effect of a nitride-based trapping storage flash EEPROM cell under two-bit operation"
    • Feb
    • Y. W. Chang, T. C. Lu, S. Pan, and C. Y. Lu, "Modeling for the second bit effect of a nitride-based trapping storage flash EEPROM cell under two-bit operation," IEEE Electron Device Lett., vol. 25, pp. 95-97, Feb. 2004.
    • (2004) IEEE Electron. Device Lett. , vol.25 , pp. 95-97
    • Chang, Y.W.1    Lu, T.C.2    Pan, S.3    Lu, C.Y.4
  • 8
    • 0035506164 scopus 로고    scopus 로고
    • "Characterization of channel hot electron injection by the subthreshold slope of NROM device"
    • Nov
    • E. Lusky, Y. Shacham-Diamand, I. Bloom, and B. Eitan, " Characterization of channel hot electron injection by the subthreshold slope of NROM device," IEEE Electron Device Lett., vol. 22, pp. 556-558, Nov. 2001.
    • (2001) IEEE Electron. Device Lett. , vol.22 , pp. 556-558
    • Lusky, E.1    Shacham-Diamand, Y.2    Bloom, I.3    Eitan, B.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.