Single-event upset in highly scaled commercial silicon-on-insulator PowerPC microprocessors

IEEE Transactions on Nuclear Science

Volumn 52, Issue 5 II, 2005, Pages 1524-1529

  Irom, F ^a   Farmanesh, F H ^a  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Cyclotron; Heavy ion; Microprocessors; Silicon on insulator (SOI)

Indexed keywords

CYCLOTRON RADIATION; ELECTRIC POTENTIAL; HEAVY IONS; MICROPROCESSOR CHIPS; THRESHOLD VOLTAGE;

CHARGE COLLECTIONS; CORE VOLTAGES;

SILICON ON INSULATOR TECHNOLOGY;

EID: 29144528878     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2005.855816     Document Type: Conference Paper

References (22)

1. G. M. Swift, F. F. Farmanesh, S. M. Guertin, F. Irom, and D. G. Millward, "Single-event upset in the power PC750 microprocessor," IEEE Trans. Nucl. Sci., vol. 48, no. 5, pp. 1822-1827, Oct. 2001.
2. R. Velazco, S. Karoui, T. Chapuis, D. Benezech, and L. H. Rosier, "Heavy ion test results for the 68 020 microprocessor and the 68 882 coprocessor," in Proc. RADECS, 1991, pp. 445-449.
3. F. Estreme et al., "SEU and latchup results for SPARC processors," in Proc. IEEE Radiation Effects Data Workshop, 1993, pp. 13-19.
4. A. Moran et al., "Single event testing of the INTEL 80 386 and the 8046 microprocessor," in Proc. RADECS, 1995, pp. 263-269.
5. F. Bezerra and J. Kuitunen, "Analysis of the SEU behavior of powerPC 603R under heavy ions," presented at the RADECS Conf. Data Workshop Record.
6. F. Bezerra et al., "Commercial processor single event tests," in Proc. RADECS Conf. Data Workshop Record, 1997, pp. 41-46.
7. D. M. Hiemstra and A. Baril, "Single-event upset characterization of the pentium MMX and pentium II microprocessors using proton irradiation," IEEE Trans. Nucl. Sci., vol. 46, no. 4, pp. 1453-1460, Aug. 1999.
8. J. P. Colinge, "Silicon-on-Insulator technology: Overview and device physics," presented at the IEEE Nuclear and Space Radiation Effects Conf. Short Course, Vancouver, BC, Canada, 2001.
9. L. W. Massengill, D. V. Kerns Jr, S. E. Kerns, and M. L. Alles, "Single-event charge enhancement in SOI devices," IEEE Electron. Device Lett., vol. 11, no. 2, pp. 98-99, Feb. 1990.
10. K. Mistry et al., "Parasitic bipolar gain reduction and the optimization of 0.25 μm partially depleted MOSFETs," IEEE Trans. Electron. Devices, vol. 46, no. 11, pp. 2201-2209, Nov. 1999.
11. S. Hareland, J. Maiz, M. Alavi, K. Mistry, S. Walsta, and C. Dai, "Impact of CMOS process scaling and SOI on the soft error rates of logic processes," in Proc. Symp. VLSI Technology, 2001, pp. 73-74.
12. P. Smeys et al., "A High Performance 0.13 μm SOI CMOS Technology with Cu Interconnects and Low-K BEOL Dielectric," in Proc. Symp. VLSI, 2000, pp. 184-185.
13. F. Irom, F. H. Farmanesh, A. H. Johnston, G. M. Swift, and D. G. Millward, "Single-event upset in commercial silicon-on-Insulator PowerPC microprocessors," IEEE Trans. Nucl. Sci., vol. 49, no. 6, pp. 3148-3155, Dec. 2002.
14. F. Irom, F. H. Farmanesh, A. H. Johnston, G. M. Swift, and G. L. Yoder, "Single-event upset in evolving commercial silicon-on-Insulator microprocessor technologies," IEEE Trans. Nucl. Sci., vol. 50, no. 4, pp. 2107-2112, Aug. 2003.
15. C. Brothers et al., "Total-Dose and SEU characterization of 0.25 micron CMOS/SOI integrated circuit memory technologies," IEEE Trans. Nucl. Sci., vol. 44, no. 4, pp. 2134-2139, Aug. 1997.
16. G. Gasiot et al., "Comparison of the sensitivity to heavy ions of 0.25 μm bulk and SOI technologies," IEEE Trans. Nucl. Sci., vol. 49, no. 3, pp. 1450-1455, Jun. 2002.
17. B. Davari, R. H. Dennard, and G. G. Shahidi, "CMOS scaling for high performance and low power-the next ten years," Proc. IEEE, vol. 83, no. 4, pp. 595-606, Apr. 1995.
18. E. L. Peterson et al., "Calculations of cosmic-ray induced upset and scaling in VLSI devices," IEEE Trans. Nucl Sci., vol. 49, no. 5, pp. 2055-2055, Oct. 1982.
19. A. H. Johnston, "Radiation effects on advanced microelectronics technologies," IEEE Trans. Nucl. Sci., vol. 45, no. 3, pp. 1339-1339, Jun. 1998.
20. P. E. Dodd et al., "SEU sensitive volumes in bulk and SOI SRAM's from first-principles calculations and experiments," IEEE Trans. Nucl. Sci., vol. 48, no. 4, pp. 1893-1903, Aug. 2001.
21. S. K. H. Fung et al., "Controlling floating body effects for 0.13 μm and 0.10 μm SOI CMOS," in Proc. IEDM Tech. Dig., 2000, pp. 231-234.
22. V. Ferlet-Cavrois et al., "Characterization of parasitic bipolar amplification in SOI technologies submitted to transient irradiation," IEEE Trans. Nucl Sci., vol. 49, no. 3, pp. 1456-1461, Jun. 2002.