Total-dose and SEU characterization of 0.25 micron CMOS/SOI integrated circuit memory technologies

IEEE Transactions on Nuclear Science

Volumn 44, Issue 6 PART 1, 1997, Pages 2134-2139

  Brothers, C ^a   Pugh, R ^a   Duggan, P ^b   Chavez, J ^b   Schepis, D ^b   Yee, D ^a   Wu, S ^b  

^a AIR FORCE RESEARCH LABORATORY   (United States)

^b IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; RADIATION EFFECTS; SILICON ON INSULATOR TECHNOLOGY;

SINGLE EVENT UPSET (SEU); STATIC RANDOM ACCESS MEMORY (SRAM);

RANDOM ACCESS STORAGE;

EID: 0031341062     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/23.659028     Document Type: Article

References (5)

1. A. J. Auberton-Herve, "SOI Technologies for High Speed and Rad-Hard Technologies: Status and Trends in VLSI and ULSI Applications," 4lh Intl. Symp. On SOI Technol. And Dev., V. 90-6, pp. 455 (1990).
2. S. T. Liu and W. C. Jenkins, "Total Dose Radiation Hard 0.5um SOI CMOS Transistors and 256K SRAMs," 1996 IEEE Radiation Effects Data Workshop, Workshop Record, pp 62-66, Jul 19, 1996.
3. A. J. Van de Goor, "Testing Semiconductor Memories: Theory and Practice", pp 117-124, John Wiley & Sons Inc., New York, 1991.
4. P. T. McDonald and W. J. Stapor, "IBM 64K-bit SRAM Heavy Ion Preliminary Results" Radiation Dynamics Memorandum, Naval Research Laboratory, Feb 26, 1996.
5. W. J. Stapor, "Single Event Effects (SEE) Qualification," 1995 IEEE Nuclear and Space Radiation Effects Conference Short Course, pp 11-44,11-60. Jul 17, 1995.