Characterization of the parasitic bipolar amplification in SOI technologies submitted to transient irradiation

IEEE Transactions on Nuclear Science

Volumn 49 III, Issue 3, 2002, Pages 1456-1461

  Ferlet Cavrois, V ^a   Marcandella, C ^a   Giraud, G ^a   Gasiot, G ^a   Colladant, T ^a   Musseau, O ^a   Fenouillet, C ^b   Du Port De Poncharra, J ^b  

^a CEA DAM DIF   (France)

^b CEA LETI   (France)

Author keywords

Parasitic bipolar transistor; Silicon on insulator (SOI) technologies; Transient irradiation

Indexed keywords

BIPOLAR TRANSISTORS; COMPUTER SIMULATION; GATES (TRANSISTOR); IRRADIATION; MOSFET DEVICES; PHOTOCURRENTS; RADIATION DAMAGE; SILICON ON INSULATOR TECHNOLOGY;

PARASITIC BIPOLAR TRANSISTOR; TRANSIENT IRRADIATION;

RADIATION HARDENING;

EID: 0036624473     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2002.1039683     Document Type: Article

References (14)

1. V. Ferlet-Cavrois et al., "Comparison of the sensitivity to heavy ions of SRAM in different SIMOX technologies," IEEE Electron Device Lett., vol. 15, pp. 82-84, Mar. 1994.
2. O. Musseau et al., "SEU in SOI SRAMs-A static model," IEEE Trans. Nucl. Sci., vol. 41, p. 607, June 1994.
3. V. Ferlet-Cavrois et al., "Transient radiation effects in CMOS/SOI transistors and circuits," in Proc. RADECS, Cannes, France, Sept. 1997, pp. 360-365.
4. C. B. Oh et al., "The effect of body contact arrangement on thin SOI MOSFET characteristics," Microelectronic Eng., vol. 28, no. 1-4, p. 467, 1995.
5. M. L. Alles et al., "Body tie placement in CMOS/SOI digital circuits for transient radiation environments," IEEE Trans. Nucl. Sci., vol. 38, p. 1259, Dec. 1991.
6. ISE (Integrated Syst. Eng.), "TCAD Manuals,", Release 6, 1999.
7. O. Flament et al., "Characterization of the parasitic bipolar transistor in SOI technology: Comparison between direct and indirect triggering techniques," in Proc. IEEE Int. Silicon-on-Insulator Conf., Wakefield, MA, Oct. 2000, p. 86.
8. O. Musseau and V. Ferlet-Cavoris, Silicon-on-insulator technologies, radiation effects (in short course NSREC 2001, Section III), July 2001.
9. TMA (Technol. Modeling Assoc.), User's Manuals, July 1996.
10. S. M. Sze, Physics of Semiconductor Devices, 2nd ed, New York: Wiley, 1981.
11. L. W. Massengill et al., "Transient radiation upset simulations of CMOS memory circuits," IEEE Trans. Nucl. Sci., vol. NS-31, p. 1337, Dec. 1984.
12. D. G. Mavis et al., "A chip-level modeling approach for rail span collapse and survivability analyses," IEEE Trans. Nucl. Sci., vol. 36, p. 2239, Dec. 1989.
13. R. Marec et al., "A new procedure for static RAM evaluation under X-ray pulses," IEEE Trans. Nucl. Sci., vol. 41, p. 2467, Dec. 1994.
14. G. Gasiot et al., "Comparison of the sensitivity to heavy ions of 0.25-μm bulk and SOI technologies," in Proc. RADECS, 2001.