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Volumn 1, Issue , 2005, Pages 647-651

Design of variable-rate irregular LDPC codes with low error floor

Author keywords

[No Author keywords available]

Indexed keywords

DECODING; ERROR DETECTION; LINEAR CONTROL SYSTEMS; REAL TIME SYSTEMS; SYSTEMS ANALYSIS;

EID: 24344498356     PISSN: 05361486     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (34)

References (18)
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  • 7
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    • Construction of short block length irregular low-density parity-check codes
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    • A. Ramamoorthy, and R. Wesel, "Construction of Short Block Length Irregular Low-Density Parity-Check Codes", Proc. IEEE International Conference on Communications, vol. 1, June 2004, pp. 410-414.
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    • Yang, M.1    Ryan, W.E.2    Li, Y.3
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    • Good error-correcting codes based on very sparse matrices
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    • D. J. C. MacKay, "Good error-correcting codes based on very sparse matrices", IEEE Transactions on Information Theory, vol. 45, Mar. 1999, pp. 399-431.
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    • MacKay, D.J.C.1
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    • 0036612281 scopus 로고    scopus 로고
    • Finite length analysis of low-density parity-check codes on the binary erasure channel
    • June
    • C. Di, D. Proietti, E. Telatar, T. Richardson, and R. Urbanke, "Finite length analysis of low-density parity-check codes on the binary erasure channel", IEEE Transactions on Information Theory, vol. 48, no. 6, June 2002, pp. 1570-1579.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.