On the use of model checking for the verification of a dynamic signature monitoring approach

IEEE Transactions on Nuclear Science

Volumn 52, Issue 5 II, 2005, Pages 1555-1561

  Nicolescu, Bogdan ^a   Gorse, Nicolas ^b   Savaria, Yvon ^a   Aboulhamid, El Mostapha ^b   Velazco, Raoul ^c  

^a ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

^b UNIVERSITÉ DE MONTRÉAL   (Canada)

^c TIMA LABORATORY   (France)

Author keywords

Fault injection; Formal verification; Model checking; Signature analysis

Indexed keywords

COMPUTER SIMULATION; ERROR DETECTION; MATHEMATICAL MODELS; NETWORKS (CIRCUITS); PROBABILITY;

FAULT INJECTION; FORMAL VERIFICATION; MODEL CHECKING; SIGNATURE ANALYSIS;

ELECTRIC FAULT CURRENTS;

EID: 29144481907     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2005.855819     Document Type: Conference Paper

References (26)

1. E. Normand, "Single event effects in avionics," IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 461-474, Apr. 1996.
2. (2003) Design. International Technology Roadmap for Semiconductor. [Online]. Available: http://public.itrs.net/Files/2003ITRS/Home2003.htm
3. N. A. Touba and E. J. McCluskey, "Logic synthesis of multilevel circuits with concurrent error detection," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 16, no. 7, pp. 783-789, Jul. 1997.
4. E. Dupont, M. Nicolaidis, and P. Rohr, "Embedded robustness ips for transient-error-free ICs," IEEE Des. Test Comput., pp. 56-70, May-Jun. 2002.
5. R. Velazco, D. Bessot, R. Eccofet, and S. Duzellier, "Two CMOS memory cells suitable for the design of SEU tolerant VLSI circuits," IEEE Trans. Nucl. Sci., vol. 6, no. 6, pp. 2229-2234, Dec. 1994.
6. N. Oh, P. Shirvani, and E. J. McCluskey, "Error detection by duplicated instructions in super-scalar processors," IEEE Trans. Reliab., vol. 51, no. 1, pp. 63-75, Mar. 2002.
7. P. Cheynet, B. Nicolescu, R. Velazco, M. Rebaudengo, M. S. Reorda, and M. Violante, "Experimentally evaluating an automatic approach for generating safety-critical software with respect to transient errors," IEEE Trans. Nucl. Sci., vol. 47, no. 6, pp. 2231-2236, Dec. 2000.
8. N. Oh, P. P. Shirvani, and E. J. McCluskey, "Control-Flow checking by software signatures," IEEE Trans. Reliab., vol. 51, no. 1, pp. 111-122, Mar. 2002.
9. G. Miremadi, J. T. J. Ohlsson, M. Rimen, and J. Karlsson, "Use of time, location and instruction signatures for control flow checking," presented at the DCCA-5 Int. Conf., 1995.
10. S. S. Yau and F. C. Chen, "An approach to concurrent control flow checking," IEEE Trans. Softw. Eng., vol. SE-6, no. 2, pp. 126-137, Mar. 1980.
11. O. Goloubeva, M. Rebaudengo, M. Sonza-Reorda, and M. Violante, "Soft-error detection using control flow assertions," in Proc. 18th IEEE Int. Symp. Defect and Fault Tolerant in VLSI Systems, Nov. 2003, pp. 581-588.
12. Z. Alkhalifa, V. S. S. Nair, N. Krishnamurthy, and J. A. Abraham, "Design and evaluation of system-level checks for on-line control flow error detection," IEEE Trans. Parallel Distrib. Syst., vol. 10, no. 6, pp. 627-641, Jun. 1999.
13. R. Velazco et al., "Predicting error rate for microprocessor-based digital architectures through C.E.U. injection," IEEE Trans. Nucl. Sci., vol. 47, no. 6, pp. 2405-2411, Dec. 2000.
14. R. Velazco, A. Corominas, and P. Ferreyra, "Injecting bit flip faults by means of a purely software approach: A case studied," in Proc. 17th IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems, Nov. 2002, pp. 108-116.
15. D. Gil, R. Martinez, J. V. Busquets, J. C. Baraza, and P. J. Gil, "Fault injection into VHDL models: Experimental validation of a fault tolerant microcomputer system," in Proc. Dependable Computing EDCC-3, Sep. 1999, pp. 191-208.
16. B. Parrotta, M. Rebaudengo, M. S. Reorda, and M. Violante, "New techniques for accelerating fault injection in VHDL descriptions," in Proc. IEEE Int. On-line Test Workshop, Jul. 2000, pp. 61-66.
17. E. Jenn, J. Arlat, M. Rimén, J. Ohlsson, and J. Karlsson, "Fault injection into VHDL models: The MEFISTO tool," in Proc. Fault-Tolerant Computing, FTCS-24, Austin, TX, 1994, pp. 66-75.
18. M. H. Chehely, M. Gasser, G. A. Huff, and K. Millen, "Verifying security," ACM Comput. Surv., vol. 13, pp. 279-339, Sep. 1981.
19. C. E. Landwehr, "Formal models for computer security," ACM Comput. Surv., vol. 13, pp. 247-278, Sep. 1981.
20. B. Nicolescu, Y. Savaria, and R. Velazco, "Software detection mechanisms providing full coverage against single bit-flip faults," IEEE Trans. Nucl. Sci., vol. 51, no. 6, pp. 3510-3518, Dec. 2004.
21. N. Oh, P. Shirvani, and E. J. McCluskey, "Error detection by duplicated instructions in super-scalar processors," IEEE Trans. Reliab., vol. 51, no. 1, pp. 63-75, Mar. 2002.
22. J. G. Holm and P. Banerjee, "Low cost concurrent error detection in a VLIW architecture using replicated instructions," in Proc. Int. Conf. Parallel Processing, 1992, pp. 192-195.
23. B. Nicolescu, Y. Savaria, and R. Velazco, "Performance evaluation and failure rate prediction for the soft implemented error detection technique," in Proc. 10th IEEE Int. On-Line Testing Symp., Madeira Island, Portugal, Jul. 2004, pp. 233-238.
24. B. Bérar et al., Systems and Software Validation, Model-Checking Techniques and Tools. New York: Springer-Verlag, 2001.
25. T. Kropf, Introduction to Formal Hardware Verification. New York: Springer-Verlag, 1999.
26. G. J. Holzmann, The SPIN Model Checker - Primer and Reference Manual. Reading, MA: Addison-Wesley, 2003.