A comparative study of the design of synchronous and asynchronous self-checking RISC processors

Proceedings - 10th IEEE International On-Line Testing Symposium, IOLTS 2004

Volumn , Issue , 2004, Pages 89-94

  Hyde, P D ^a   Russell, G ^a  

^a NEWCASTLE UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CHECK SYMBOL GENERATOR (CSG); CONCURRENT ERROR DETECTION (CED); MODIFIED BERGER (MB) CODES; TOTALLY SELF CHECKING (TSC);

CAPACITANCE; COMPUTATIONAL GEOMETRY; DATA TRANSFER; ERROR DETECTION; FREQUENCIES; LOGIC GATES; MICROPROCESSOR CHIPS; RELIABILITY; TRANSISTORS; VLSI CIRCUITS;

REDUCED INSTRUCTION SET COMPUTING;

EID: 10444222528     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2004.1319664     Document Type: Conference Paper

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