Gate-all-around MOSFETs: Lateral ultra-narrow (≤10 nm) fin as channel body

Electronics Letters

Volumn 41, Issue 24, 2005, Pages 1353-1354

  Singh, N ^a   Agarwal, A ^a   Bera, L K ^a   Kumar, R ^a   Lo, G Q ^a   Narayanan, B ^a   Kwong, D L ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTROSTATICS; LITHOGRAPHY; LOW TEMPERATURE EFFECTS; OXIDATION; SILICON;

DUV LITHOGRAPHY; ELECTROSTATIC CONTROL; GATE ELECTROSTATICS; TEMPERATURE OXIDATION;

MOSFET DEVICES;

EID: 28444432005     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20053195     Document Type: Article

References (9)

1. Hu, C.: ' Device challenges and opportunities ', VLSI Tech. Symp., 2004, p. 4-5
2. Hisamoto, D., Lee, W.-C., Kedzierski, J., Takeuchi, H., Asano, K., Kuo, C., Anderson, E., King, T.-J., Bokor, J., and Hu, C.: ' FinFET - a self-aligned double-gate MOSFET scalable to 20 nm ', IEEE Trans. Electron Devices, 2002, 47, (12), p. 2320-2325
3. Doyle, B., Datta, S., Doczy, M., Hareland, S., Jin, B., Kavalieros, J., Linton, T., Murthy, A., Rios, R., and Chau, R.: ' High performance fully-depleted tri-gate CMOS transistor ', IEEE Electron Device Lett., 2003, 24, (4), p. 263-265
4. Park, J.T., Colinge, J.-P., and Diaz, C.H.: ' Pi-gate SOI MOSFET ', IEEE Electron Device Lett., 2001, 22, (8), p. 405-406
5. Yang, F.-L., Chen, H.Y., Chen, F.C., Huang, C.C., Chang, C.Y., Chiu, H.K., Lee, C.C., Chen, C.C., Huang, H.T., Chen, C.J., Tao, H.J., Yeo, Y.C., and Hu, C.: ' 25 nm CMOS Omega FETs ', IEDM Tech. Dig., 2002, p. 255-258
6. Colinge, J.P., Gao, M.H., Rodriguez, A.R., Maes, H., and Claeys, C.: ' Silicon-on-insulator: gate-all-around device ', IEDM Tech. Dig., 1990, p. 595-598
7. Monfray, S., Skotniki, T., Morand, Y., Descombes, S., Coronel, P., Mazoyer, P., Harrison, S., Ribot, P., Talbot, A., Dutartre, D., Haond, M., Palla, R., Le Friec, Y., Leverd, F., Nier, M.E., Vizioz, C., and Louis, D.: ' 50 nm-gate all around (GAA) - silicon on nothing (SON) - devices: a simple way to co-integration of GAA transistors with bulk MOSFET process ', VLSI Technology Symp., 2002, p. 108-109
8. Park, J.-T., and Colinge, J.-P.: ' Multiple-gate SOI MOSFETs: device design guidelines ', IEEE Trans. Electron Devices, 2002, 49, (12), p. 2222-2229
9. Auth, C.P., and Plummer, J.D.: ' Scalling theory for cylindrical, fully-depleted, surrounding-gate MOSFETs ', IEEE Electron Device Lett., 1997, 18, (2), p. 74-76