A low-jitter 5000ppm spread spectrum clock generator for multi-channel SATA transceiver in 0.18μm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Lee, Hyung Rok ^a,b   Kim, Ook ^b   Ahn, Gijung ^b   Jeong, Deog Kyoon ^a  

^a Seoul National University   (South Korea)

^b Silicon Image Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144457198     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2005.1493919     Document Type: Conference Paper

References (7)

1. Serial ATA Workgroup, "Serial ATA II: Electrical Specification," Revision 1.0, May, 2004.
2. M. Sugawara et al., "1.5 Gb/s, 5150 ppm Spread Spectrum SerDes PHY with a 0.3mW, 1.5Gb/s Level Detector for Serial ATA," Symp. VLSI Circuits, pp. 60-63, June, 2002.
3. M. Aoyama et al., "3 Gb/s, 5000ppm Spread Spectrum SerDes PHY with Frequency Tracking Phase Interpolator for Serial ATA," Symp. VLSI Circuits, pp. 107-110, June, 2003.
4. K. Lee et al., "A CMOS Serial Link for Fully Duplexed Data Communication," IEEE J. Solid-State Circuits, vol. 30, pp. 353-364, Apr., 1995.
5. C.H. Heng and B.S. Song, "A 1.8-GHz CMOS Fractional-N Frequency Synthesizer with Randomized Multiphase VCO," IEEE J. Solid-State Circuits, vol. 38, pp. 848-854, June, 2003.
6. K.B. Hardin et al., "Design Considerations of Phase-Locked Loop Systems for Spread Spectrum Clock Generation Compatibility," IEEE Intl. Symp. on Electromagnetic Compatibility, pp. 302-307, Aug., 1997.
7. M. H. Perrott, "Fast and Accurate Behavioral Simulation of Fractional-N Frequency Synthesizers and Other PLL/DLL Circuits," Design Automation Conference, pp. 498-503, June, 2002.