1.5 Gbps, 5150 ppm spread spectrum SerDes PHY with a 0.3 mW, 1.5 Gbps level detector for serial ATA

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 60-63

  Sugawara, Mitsutoshi ^a   Ishibashi, Terukazu ^a   Ogasawara, Kazuo ^b   Aoyama, Morishige ^b   Zwerg, Michael ^a   Glowinski, Steven ^a   Kameyama, Yukihiro ^a   Yanagita, Tomonori ^a   Fukaishi, Muneo ^b   Shimoyama, Shinichi ^a   Ishibashi, Takashi ^a   Noma, Toshihoro ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

^b NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; DESIGN FOR TESTABILITY; ELECTRIC CURRENT MEASUREMENT; PHASE LOCKED LOOPS; SPREAD SPECTRUM COMMUNICATION; TIMING CIRCUITS;

PHYSICAL LAYER CHIP; SPREAD SPECTRUM DESERIALIZER CHIP; SPREAD SPECTRUM SERIALIZER CHIP;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0242443405     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)

1. Klaus-Peter Deyring "Proposed Draft rev.1.0.0.0, Serial ATA/High Speed Selialized AT Attachment", Serial ATA Workgroup, Nov/2000