Optimization of shear test for flip chip solder bump using 3-dimensional computer simulation

Microelectronic Engineering

Volumn 82, Issue 3-4 SPEC. ISS., 2005, Pages 554-560

  Kim, Jong Woong ^a   Jung, Seung Boo ^a  

^a Sungkyunkwan University   (South Korea)

Author keywords

Finite element analysis; Flip chip; Shear height; Shear speed

Indexed keywords

COMPUTER SIMULATION; FINITE ELEMENT METHOD; FRACTURE; OPTIMIZATION; SHEAR STRESS; SOLDERED JOINTS;

FLIP CHIP SOLDER; SHEAR HEIGHT; SHEAR SPEED;

FLIP CHIP DEVICES;

EID: 28144449941     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2005.07.055     Document Type: Conference Paper

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