A 220mW 1Gb/s 1024-Bit Rate-1/2 Low Density Parity Check Code Decoder

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2001, Pages 293-296

  Howland, C ^a   Blanksby, A ^a  

^a AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODING ERRORS; DECODING; ELECTRIC POWER SUPPLIES TO APPARATUS; GAIN MEASUREMENT; SWITCHING CIRCUITS; TURBO CODES;

CODING GAIN; DECODER; LOW DENSITY PARITY CHECK CODE; POWER DISSIPATION;

POWER INTEGRATED CIRCUITS;

EID: 0034834939     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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6. Iterative decoding of compound codes by probability propagation in graphical models
7. Parallel decoding architectures for low density parity check codes
8. A viterbi algorithm with soft-decision outputs and its applications
9. Optimal decoding of linear codes for minimizing symbol error rate