VLSI implementation for low density parity check decoder

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 3, Issue , 2001, Pages 1223-1226

  Lee, W L ^a   Wu, Angus ^a  

^a CITY UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

COMPLEX OPERATIONS; COMPUTER AIDED DESIGN TOOLS; DECISION LOGIC; IN-PLACE ALGORITHMS; INTERMEDIATE STORAGE; LOOK UP TABLE; LOW COMPLEXITY; LOW DENSITY PARITY CHECK; PERSONAL COMMUNICATIONS; SYNOPSYS; TURBO CODE DECODERS; VLSI DECODER ARCHITECTURES; VLSI IMPLEMENTATION;

COMPUTER AIDED DESIGN; COMPUTER HARDWARE DESCRIPTION LANGUAGES; FREQUENCY SELECTIVE FADING; SATELLITE COMMUNICATION SYSTEMS; TABLE LOOKUP; VLSI CIRCUITS;

DECODING;

EID: 31344445796     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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8. Sangjin Hong and Wayne E. Stark, "VLSI Circuit Complexity and Decoding Performance Analysis for Low-power RSC Turbo-code and Iterative Block Decoders Design," Proc. of the IEEE Military Communications Conf., vol. 3, 1998, pp. 708-712.