Variable input delay CMOS logic for low power design

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2005, Pages 598-605

  Raja, Tezaswi ^a   Agrawal, Vishwani D ^b   Bushnell, Michael L ^c  

^a Transmeta Corporation   (United States)

^b AUBURN UNIVERSITY   (United States)

^c RUTGERS UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; DELAY BUFFERS; LOW POWER DESIGN;

DIGITAL CIRCUITS; DYNAMICS; LINEAR PROGRAMMING; LOGIC DESIGN; LOGIC GATES; TRANSISTORS;

CMOS INTEGRATED CIRCUITS;

EID: 27944486557     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.2005.167     Document Type: Conference Paper

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