CMOS circuit design for minimum dynamic power and highest speed

Proceedings of the IEEE International Conference on VLSI Design

Volumn 17, Issue , 2004, Pages 1035-1040

  Raja, Tezaswi ^a   Agrawal, Vishwani D ^a,b   Bushnell, Michael L ^a  

^a RUTGERS UNIVERSITY   (United States)

^b AUBURN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; GATES (TRANSISTOR); LINEAR PROGRAMMING; NAND CIRCUITS;

MINIMUM TRANSIENT ENERGY (MTE); POWER DISSIPATION; SIGNAL TRANSITIONS;

PRINTED CIRCUIT DESIGN;

EID: 2342473809     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (26)

1. V. D. Agrawal, "Low Power Design by Hazard Filtering," in Proc. of the International Conference on VLSI Design, Jan. 1997, pp. 193-197.
2. V. D. Agrawal, M. L. Bushnell, G. Parthasarathy, and R. Ramadoss, "Digital Circuit Design for Mimimum Transient Energy and Linear Programming Method," in Proc. of the International Conference on VLSI Design, Jan. 1999, pp. 434-439.
3. M. Berkelaar, P. Buurman, and J. Jess, "Computing Entire Area/Power Consumption versus Delay Trade-off Curve for Gate Sizing Using a Piecewise Linear Simulator," IEEE Transactions on Circuits and Systems, vol. 15, no. 11, pp. 1424-1434, Nov. 1996.
4. M. Berkelaar and E. Jacobs, "Using Gate Sizing to Reduce Glitch Power," in Proc. of the Pro RISC Workshop on Circuits, Systems and Signal Processing, (Mierlo, The Netherlands), Nov. 1996, pp. 183-188.
5. M. Berkelaar and J. A. G. Jess, "Transistor Sizing in MOS Digital Circuits with Linear Programming," in Proc. of the European Design Automation Conference, (Mierlo, The Netherlands), Mar. 1990, pp. 217-221.
6. M. Borah, M. J. Irwin, and R. M. Owens, "Minimizing Power Consumption of Static CMOS Circuits by Transistor Sizing and Input Reordering," in Proc. of the International Conference on VLSI Design, Jan. 1995, pp. 294-298.
7. A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design. Boston: Kluwer Academic Publishers, 1995.
8. W. Chuang, S. S. Sapatnekar, and I. N. Hajj, "A Unified Algorithm for Gate Sizing and Clock Skew Optimization to Minimize Sequential Circuit Area," in Proc. of the International Conference on Computer-Aided Design, Nov. 1993, pp. 220-223.
9. W. Chuang, S. S. Sapatnekar, and I. N. Hajj, "Timing and Area Optimization for Standard Cell VLSI Circuit Design," IEEE Transactions on Computer-Aided Design, vol. 14, no. 3, pp. 308-320, Mar. 1995.
10. S. Datta, S. Nag, and K. Roy, "ASAP: A Transistor Sizing Tool for Area, Delay and Power Optimization of CMOS Circuits," in Proc. of the IEEE International Symposium on Circuits. and Systems, May 1994, pp. 61-64.
11. M. S. Elrabaa, I. S. Abu-Khater, and M. I. Elmasry, Advanced Low-Power Digital Circuit Techniques. Boston: Kluwer Academic Publishers, 1997.
12. J. P. Fishburn and A. E. Dunlop, "TILOS: A Posynomial Programming Approach to Transistor Sizing," in Proc. IEEE International Conf. Computer-Aided Design, Nov. 1985, pp. 326-328.
13. R. Fourer, D. M. Gay, and B. M. Kernighan, AMPL: A Modeling Language for Mathematical Programming. South San Francisco, California: The Scientific Press, 1993.
14. R. B. Hitchcock Sr., "Timing Verification and the Timing Analysis Program," in Proc. of the 19th Design Automation Conf., June 1982, pp. 594-604.
15. R. B. Hitchcock Sr., G. L. Smith, and D. C. Cheng, "Timing Analysis of Computer Hardware," IBM Journal of Research & Development, vol. 26, no. 1, pp. 100-105, Jan. 1982.
16. M. Hsiao, E. M. Rudnick, and J. H. Patel, "Effects of Delay Model in Peak Power Estimation of VLSI Circuits," in Proc. of the International Conference on Computer-Aided Design, Nov. 1997, pp. 45-51.
17. J. Monteiro and S. Devadas, Computer-Aided Design Techniques for Low Power Sequential Logic Circuits. Boston: Kluwer Academic Publishers, 1997.
18. J. M. Rabaey and M. Pedram, Low Power Design Methodologies. Boston: Kluwer Academic Publishers, 1995.
19. T. Raja, "A Reduced Constraint Set Linear Program for Low Power Design of Digital Circuits," Master's thesis, Rutgers University, Dept. of ECE, Piscataway, New Jersey, May 2002.
20. T. Raja, V. D. Agrawal, and M. L. Bushnell, "Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program," in Proc. of the International Conference on VLSI Design, Jan. 2003, pp. 527-532.
21. K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit Design. New York: Wiley Interscience Publication, 2000.
22. C. V. Schimpfle, A. Wroblewski, and J. A. Nassek, "Transistor Sizing for Switching Activity Reduction in Digital Circuits," in Proc. of the European Conference on Theory and Design, Aug. 1999.
23. J. M. Shyu, A. L. Sangiovanni-Vincntelli, J. P. Fishburn, and A. E. Dunlop, "Optimization-based Transistor Sizing ," IEEE Journal of Solid-State Circuits, vol. 23, no. 2, pp. "400-409", Apr. 1988.
24. V. Sundararajan, S. Sapatnekar, and K. Parhi, "Fast and Exact Transistor Sizing Based on Iterative Relaxation," IEEE Transactions on Computer Aided Design of Circuits and Systems, vol. 21, 2002.
25. S. H. linger, Asynchronous Sequential Switching Circuits. New York: Wiley-Interscience, 1969.
26. A. Wroblewski, C. V. Schimpfle, and J. A. Nassek, "Automated Transistor Sizing Algorithm for Minimizing Spurious Switching Activities in CMOS Circuits," in Proc. of the IEEE International Symposium on Circuits and Systems, May 2000.