Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-μ/m CMOS integrated circuits

IEEE International Reliability Physics Symposium Proceedings

Volumn 2004-January, Issue January, 2004, Pages 381-386

  Ker, Ming Dou ^a   Hsu, Kuo Chun ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

CDM; ESD; ESD protection circuit; HBM; Latchup; SCR

Indexed keywords

ELECTROSTATIC DEVICES; ELECTROSTATIC DISCHARGE; MOS DEVICES; SEMICONDUCTOR JUNCTIONS; THYRISTORS; VOLTAGE CONTROL;

CDM; ESD; ESD PROTECTION CIRCUIT; HBM; LATCH-UPS;

CMOS INTEGRATED CIRCUITS;

EID: 27844508760     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2004.1315356     Document Type: Conference Paper

References (8)

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7. M.-D. Ker and K.-C. Hsu, "SCR devices with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes," IEEE Trans, on Device and Materials Reliability, vol. 3, no. 3, pp. 58-68, Sept. 2003.
8. M.-D. Ker, C.-Y. Chang, and H.-C. Jiang, "Design of negative charge pump circuit with polysilicon diodes in a 0.25-μm CMOS process," in Proc. IEEE AP-ASIC Conference, 2002, pp. 145-148.