Design of a low power wide-band high resolution programmable frequency divider

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 9, 2005, Pages 1098-1103

  Yu, X P ^a   Do, M A ^a   Jia, L ^a   Ma, J G ^a   Yeo, K S ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

CMOS digital integrated circuits; Flip flops; Frequency dividers; Frequency synthesizers; Phase locked loops

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; FLIP FLOP CIRCUITS; FREQUENCY SYNTHESIZERS; OPTIMIZATION; PHASE LOCKED LOOPS;

CMOS DIGITAL INTEGRATED CIRCUITS; POWER CONSUMPTION; PROPAGATION DELAY;

FREQUENCY DIVIDING CIRCUITS;

EID: 27844438606     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2005.857153     Document Type: Review

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