GHz programmable counter with low power consumption

Electronics Letters

Volumn 39, Issue 22, 2003, Pages 1572-1573

  Do, M A ^a   Yu, X P ^a   Ma, J G ^a   Yeo, K S ^a   Wu, R ^a   Zhang, Q X ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ENERGY UTILIZATION; FLIP FLOP CIRCUITS; MOS CAPACITORS;

FREQUENCY DIVIDERS; PROGRAMMABLE COUNTERS;

CMOS INTEGRATED CIRCUITS;

EID: 0242721395     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20031022     Document Type: Article

References (4)

1. WU, J.C., and CHANG, H.H.: 'A 550 MHz 9.3 mW CMOS frequency divider'. IEEE Int. Symp. on Circuits and systems, 1995, Seattle, WA, USA, 1995, Vol. 1, pp. 199-202
2. CHANG, H.H., and WU, J.C.: 'A 723-MHz 17.2-mW CMOS programmable counter', IEEE J. Solid-State Circuits, 1998, 33, (10), pp. 1572-1575
3. YEO, K.S., ROFAIL, S.S., and GOH, W.L.: 'CMOS/BiCMOS ULSI: low-voltage low-power' (Prentice-Hall, Upper Saddle River, NJ, Professional Technical Reference, International Edition, 2002)
4. LARSSON, P.: 'High-speed architecture for a programmable frequency divider and a dual modulus prescaler', IEEE J. Solid-State Circuits, 1996, 31, (5), pp. 744-748