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Volumn 2002-January, Issue , 2002, Pages 111-116

Spectrum-based BIST in complex SOCs

Author keywords

Built in self test

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; INTEGRATED CIRCUIT TESTING; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM-ON-CHIP;

EID: 27744543625     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2002.1011120     Document Type: Conference Paper
Times cited : (5)

References (11)
  • 2
    • 0024934580 scopus 로고
    • Test set embedding in a built-in-self-test environment
    • S. B. Akers and W. Jansz. Test set embedding in a built-in-self-test environment. Proc. Intl Test Conf., pp. 257-263, 1989.
    • (1989) Proc. Intl Test Conf. , pp. 257-263
    • Akers, S.B.1    Jansz, W.2
  • 6
    • 0034994832 scopus 로고    scopus 로고
    • Novel spectral methods for built-in self-test in a system-on-a-chip environment
    • A. S. Giani, S. Sheng, M. Hsiao, and V. D. Agrawal. Novel spectral methods for built-in self-test in a system-on-a-chip environment. Proc. VLSI Test Symp., pp. 163-168, 2001.
    • (2001) Proc. VLSI Test Symp. , pp. 163-168
    • Giani, A.S.1    Sheng, S.2    Hsiao, M.3    Agrawal, V.D.4
  • 7
    • 84961240995 scopus 로고
    • Generation of vector patterns through reseeding of multiple polynomial linear feedback shift registers
    • S. Hellebrand, S. Tarnick, J. Rajski, and B. Courtois. Generation of vector patterns through reseeding of multiple polynomial linear feedback shift registers. Proc. Intl Test Conf.,pp. 120-129, 1992.
    • (1992) Proc. Intl Test Conf. , pp. 120-129
    • Hellebrand, S.1    Tarnick, S.2    Rajski, J.3    Courtois, B.4
  • 9
    • 0029713988 scopus 로고    scopus 로고
    • Generating deterministic unordered test patterns with counter
    • D. Kagaris and S. Tragoudas. Generating deterministic unordered test patterns with counter. Proc. VLSI Test Symp., pp. 374-379, 1996.
    • (1996) Proc. VLSI Test Symp. , pp. 374-379
    • Kagaris, D.1    Tragoudas, S.2
  • 11
    • 0031276326 scopus 로고    scopus 로고
    • Arithmetic built-in-self-test for DSP cores
    • November
    • K. Radecja, J. Rajski, and J. Tyszer. Arithmetic built-in-self-test for DSP cores. IEEE Trans. on CAD, 16(11):1358-1369, November 1997.
    • (1997) IEEE Trans. on CAD , vol.16 , Issue.11 , pp. 1358-1369
    • Radecja, K.1    Rajski, J.2    Tyszer, J.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.