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Volumn I, Issue , 2005, Pages 366-371

Design space exploration for dynamically reconflgurable architectures

Author keywords

[No Author keywords available]

Indexed keywords

DATA FLOW GRAPHS; DYNAMICALLY RECONFLGURABLE ARCHITECTURES; EMBEDDED SYSTEM ARCHITECTURES; SEARCH ALGORITHMS;

EID: 27644595222     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.118     Document Type: Conference Paper
Times cited : (16)

References (15)
  • 3
    • 33646931959 scopus 로고    scopus 로고
    • Partitioning and codesign tools & methodology for reconfigurable computing: The EPICURE philosophy
    • July
    • M. Auguin and K. Ben Chehida et al. Partitioning and codesign tools & methodology for reconfigurable computing: the EPICURE philosophy. In Proc. 3rd Workshop on Systems, Architectures, Modeling Simulation, pages 46-51, July 2003.
    • (2003) Proc. 3rd Workshop on Systems, Architectures, Modeling Simulation , pp. 46-51
    • Auguin, M.1    Ben Chehida, K.2
  • 5
    • 84956862038 scopus 로고    scopus 로고
    • Hardware-software codesign for dynamically reconfigurable architectures
    • P. Lysaght et al., editor. Springer-Verlag, Berlin
    • K. S. Chatha and R. Vemuri. Hardware-software codesign for dynamically reconfigurable architectures. In P. Lysaght et al., editor. Field-Programmable Logic and Applications, pages 175-184. Springer-Verlag, Berlin, 1999.
    • (1999) Field-programmable Logic and Applications , pp. 175-184
    • Chatha, K.S.1    Vemuri, R.2
  • 8
    • 0032681537 scopus 로고    scopus 로고
    • An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications
    • M. Kaul, R. Vemuri, S. Govindarajan, and I. Ouaiss. An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications. In Proc. of Design Automation Conf., pages 616-622, 1999.
    • (1999) Proc. of Design Automation Conf. , pp. 616-622
    • Kaul, M.1    Vemuri, R.2    Govindarajan, S.3    Ouaiss, I.4
  • 12
    • 0036705054 scopus 로고    scopus 로고
    • HW/SW codesign techniques for dynamically reconfigurable architectures
    • August
    • J. Noguera and R. Badia. HW/SW codesign techniques for dynamically reconfigurable architectures. IEEE Transactions on VLSI Systems. 10(4):399-115. August 2002.
    • (2002) IEEE Transactions on VLSI Systems , vol.10 , Issue.4 , pp. 399-1115
    • Noguera, J.1    Badia, R.2
  • 14
    • 84962312624 scopus 로고    scopus 로고
    • Hardware-software co-synthesis of low power real-time distributed embedded systems with dynamically reconfigurable FPGAs
    • Jan.
    • E. Shang and N. K. Jha. Hardware-software co-synthesis of low power real-time distributed embedded systems with dynamically reconfigurable FPGAs. In 15th IEEE Intnl. Conf. on VLSI Design, pages 345-352, Jan. 2002.
    • (2002) 15th IEEE Intnl. Conf. on VLSI Design , pp. 345-352
    • Shang, E.1    Jha, N.K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.