Decoupled dynamic ternary content addressable memories

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 52, Issue 10, 2005, Pages 2139-2147

  Delgado Frias, José G ^a   Nyathi, Jabulani ^a   Tatapudi, Suryanarayana B ^a  

^a Washington State University   (United States)

Author keywords

Content addressable memory (CAM); Dynamic circuits; Memory cells; Ternary digit (trit) operations; Ternary matching

Indexed keywords

ALGORITHMS; CACHE MEMORY; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; TRANSISTORS;

DYNAMIC CIRCUITS; MEMORY CELLS; TERNARY CONTENT ADDRESSABLE MEMORIES; TERNARY DIGIT OPERATIONS; TERNARY MATCHING;

ASSOCIATIVE STORAGE;

EID: 27644512082     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2005.853358     Document Type: Article

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