A programmable dynamic interconnection network router with hidden refresh

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 45, Issue 11, 1998, Pages 1182-1190

  Delgado Frias, José G ^a   Nyathi, Jabulani ^b   Summerville, Douglas H ^a,b  

^a State University of New York at Binghamton   (United States)

^b University of Hawaii at Manoa   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC CIRCUITS; PARALLEL ALGORITHMS; PARALLEL PROCESSING SYSTEMS; SEMICONDUCTOR STORAGE; TRANSISTORS; VLSI CIRCUITS;

DYNAMIC CONTENT ADDRESSABLE MEMORY (DCAM); PROGRAMMABLE PIPELINED ROUTERS; TERNARY DIGIT LOGIC;

ROUTERS;

EID: 0032204642     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.735440     Document Type: Article

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