A hybrid wave pipelined network router

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 49, Issue 12, 2002, Pages 1764-1772

  Nyathi, Jabulani ^a   Delgado Frias, José G ^a  

^a Washington State University   (United States)

Author keywords

Bit pattern associative memory; Computer network address decoder; Delay balancing; Dynamic ternary content addressable memory; Hybrid wave pipelining; Wave pipelined clock

Indexed keywords

ALGORITHMS; ASSOCIATIVE STORAGE; COMPUTER SIMULATION; CONGESTION CONTROL (COMMUNICATION); DATA COMMUNICATION SYSTEMS; DECODING; INTEGRATED CIRCUIT MANUFACTURE; OPTIMIZATION; PIPELINE PROCESSING SYSTEMS; TABLE LOOKUP; VLSI CIRCUITS;

BIT PATTERN ASSOCIATIVE ROUTER; COMPUTER NETWORK ADDRESS DECODER; DELAY BALANCING; HYBRID WAVE PIPELINING; ROUTING ALGORITHMS; WAVE PIPELINED CLOCK;

ROUTERS;

EID: 0036964475     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2002.805705     Document Type: Article

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