Noise characterization of the 0.35 μm CMOS analog process implemented in regular and SOI wafers

11th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2004

Volumn , Issue , 2004, Pages 171-174

  Brouk, I ^a   Nemirovsky, Y ^a  

^a TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

PROCESS CONTROL; SILICON ON INSULATOR TECHNOLOGY; SPURIOUS SIGNAL NOISE; CMOS INTEGRATED CIRCUITS;

CMOS PROCESS; NOISE MEASUREMENTS; SOI WAFERS;

CMOS INTEGRATED CIRCUITS; SILICON WAFERS;

1/F NOISE; 1/F-NOISE; ANALOG APPLICATIONS; BIAS CONDITIONS; CMOS ANALOG PROCESS; MEASUREMENTS OF; NOISE CHARACTERIZATION; NOISE MEASUREMENTS; SOI WAFERS; SUBTHRESHOLD;

EID: 27644493682     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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