SOI power devices

Electronics and Communication Engineering Journal

Volumn 12, Issue 1, 2000, Pages 27-40

  Udrea, Florin ^a   Garner, David ^b   Sheng, Kuang ^b   Popescu, Anca ^b   Lim, Hong Tee ^b   Milne, W I ^b   Milne, Bill ^b  

^a UNIVERSITY OF CAMBRIDGE   (United Kingdom)

^b NONE

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; POWER INTEGRATED CIRCUITS;

SILICON ON INSULATOR (SOI) SWITCHING DEVICES;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0033886882     PISSN: 09540695     EISSN: None     Source Type: None    
DOI: 10.1049/ecej:20000104     Document Type: Article

References (34)

1. WARMERDAN, L., and PUNT, W.: 'High-voltage SOI for single-chip power', Eur. Semicond., June 1999, pp. 19-20
2. MERCHANT, S., ARNOLD, E., BAUMGART, H., MUKHERJEE, S., PEIN, H., and PINKER, R.: 'Realization of high breakdown voltage (> 700 V) in thin SOI devices'. Proc. IEEE Int. Symp. on Power Semiconductors and ICs, ISPSD'91, pp. 31-35
3. LETAVIC, T., SIMPSON, M., ARNOLD, E., PETERS, E., AQUINO, R., CURCIO, J., HERKO, S., and MUKHERJEE, S.: '600 V power conversion system-on-a chip based on thin layer silicon-on-insulator'. Proc. ISPSD'99, (IEEE, 1999), pp. 325-328
4. NAKAGAWA, A.: 'Impact of dielectric isolation technology on power ICs'. Proc. ISPSD'91, (IEEE, 1991), pp. 16-21
5. RATNAM, P.: 'Novel silicon-on-insulator MOSFET for high-voltage integrated circuits', Electron. Lett., 1989, 25, (8), pp. 536-537
6. UDREA, F., MILNE, W. I., and POPESCU, A.: 'A new LIGBT structure based on partial isolation SOI technology', Electron. Lett., May 1997, 33, (10), p. 907
7. GARNER, D. M., ENSELL, G., BONAR, J., BLACKBURN, A., UDREA, F., LIM, H. T., POPESCU, A., HEMMENT, P. L. F., and MILNE, W. I.: The fabrication of a partial SOI substrate'. 9th Int. Symp. on Silicon-on-Insulator Technology and Devices, (The Electrochemical Society, 1999), pp. 73-78
8. UDREA, F., POPESCU, A., and MILNE, W. I.: The 3D RESURF double-gate MOSFET: a revolutionary power device concept', Electron. Lett., April 1998, 34, (8), p. 808
9. UDREA, F.: '3D semiconductor devices'. Japanese Patent No. 98P01676
10. MATSUMURA, A., KAWAMURA, K., MIZUTANI, T., TAKAYAMA, S., HAMAGUCHI, I., and NAGATAKE, Y.: 'Recent progress in low-dose SIMOX wafers fabrication with internal-thermal-oxidation (ITOX) process'. 9th Int. Symp. on Silicon-on-Insulator Technology and Devices, (The Electrochemical Society, 1999), pp. 79-92
11. LASKY, J. B.: Wafer bonding for silicon-on-insulator technologies', Appl. Phys. Lett., 1986, 48, (1), pp. 78-80
12. AUBERTON-HERVE, A. J., GHYSELEN, B., LETERTRE, F., MALEVILLE, C., BARGE, T., and BRUEL, M.: 'Smart Cut technology: industrial status of SOI wafer production and new material developments'. 9th Int. Symp. on Silicon-on-Insulator Technology and Devices, (The Electrochemical Society, 1999), pp. 93-106
13. COLINGE, J-P.: 'Silicon-on-insulator technology: materials to VLSI' (Kluwer Academic Publishers, 1997, 2nd edn.)
14. SUNKAVALLI, R., BALIGA, B. J., HUANG, Y. S.: 'High temperature performance of LDMOSFET, LIGBT and LEST'. Int. Electron Devices Meeting (IEDM) Tech. Digest, (IEEE, 1933), pp.683-686
15. DISNEY, D., and PLUMMER, J.: 'Fast switching LIGBT devices fabricated on SOI substrates'. Proc. ISPSD'92, (IEEE, 1992) ,pp. 48-51
16. MATSUDAI, T., KITAGAWA, M., and NAKAGAWA, A.: 'A trench-gate injection enhanced lateral IEGT on SOI'. Proc. ISPSD'95, (IEEE, 1995), pp. 141-145
17. DISNEY, D., PEIN, H. B., and PLUMMER, J.: 'A trench gate LIGBT structure and two LMCT structures in SOI substrates'. Proc. ISPSD'94, (IEEE, 1994), pp. 405-410
18. COLINGE, J-P., and CHIANG, S. Y.: 'A lateral COMFET made in thin silicon-on-insulator film', IEEE Electron Device Lett., 1986, 7, (12), pp.697-699
19. GARNER, D. M., UDREA, F., LIM, H. T., and MILNE, W.I.: 'An analytic model for turn off in the silicon-on-insulator LIGBT', Solid-State Electron., 1999, 43, (10), pp. 1855-1868
20. APPELS, J. A. and VAES: 'High-voltage thin layer devices (RESURF Devices)'. IEDM Tech. Digest, (IEEE, 1979), pp.238-241
21. HUANG, Y. S., and BALIGA, B. J.: 'Extension of RESURF principle to dielectrically isolated power devices'. Proc. ISPSD'91, (IEEE, 1991), pp. 27-30
22. ARNOLD, E., PEIN, H., and HERKO, S. P.: 'Comparison of self-heating effects in bulk-silicon and SOI high-voltage devices'. IEDMTech. Digest, (IEEE, 1994), pp. 813-816
23. LEUNG, Y. K., KUEHNE, S. C., HUANG, V. S. K., NGUYEN, C. T., PAUL, A. K., PLUMMER, J. D., and WONG, S. S.: 'Spatial temperature profiles due to nonuniform self-heating in LDMOS's in thin SOI', IEEE Electron Device Lett., 1996, 187, (1), pp.13-15
24. LIM, H. T., UDREA, F., GARNER, D. M., and MILNE, W. I.: 'Modelling of self-heating effect in thin SOI and Partial SOI LDMOS power devices', Solid State Electron., 1999, 43, pp. 1267-1280
25. JAUME, D., CHARITAT, G., REYNES, M., and ROSSEL, P.: 'High-voltage planar devices using field plate and semi-resistive layers', IEEE Trans. Electron Devices, July 1991, 38, (7), pp. 1681-1684
26. CHARITAT, G., BOUANANE, M. A., and ROSSEL, P.: 'A new junction termination technique for power devices: RESURF LDMOS with SIPOS layers'. Proc. ISPSD'92, (IEEE, 1992), pp. 213-216
27. MATSUDAI, T., and NAKAGAWA, A.: 'Simulation of a 700 V high-voltage device structure on a thin SOI -substrate bias effect on SOI devices'. Proc. ISPSD'92, (IEEE, 1992), pp. 272-277
28. VESTLING, L., EDHOLM, B., OLSSON, J., TIENSUU, S., and SODERBARG, A.: 'A novel high frequency high-voltage LDMOS transistor using an extended gate RESURF technology'. Proc. ISPSD'97, (IEEE, 1997), pp. 45-48
29. NARAYANAN, E. M. S., AMARATUNGA, G. A J., and MILNE, W. I.: 'A new double dielectric isolation technology for HVICs'. Proc. ISPSD'93, (IEEE, 1993), pp. 113-118
30. FUJIHIRA, T., and MIYASAKA, Y.: 'Simulated superior performances of semiconductor superjunction devices'. Proc. ISPSD'98, (IEEE, 1998), pp. 423-426
31. LORENZ, L., DEBOY, G., MÄRZ, M., STENGL, J.-P., and BACHOFNER, A.: 'Drastic reduction of ON-Resistance with CoolMos', PCIM Europe, 5, 1998, pp. 250-258
32. ARNOLD, E., MERCHANT, S., AMATO, M., MURKHERJEE, S., and PEIN, H.: 'Comparison of junction-isolated and SOI high-voltage devices operating in the source-follower mode'. Proc. 4th Int. Symp. on Power Semiconductor Devices and ICs, ISPSD'92, (IEEE, 1992), pp. 242-243
33. SUMIDA, H., HIRABAYASHI, A., SHIMABUKURO, H., TAKAZAWA, Y., and SHIGETA, Y.: 'A high performance plasma display panel driver IC using SOI'. Proc. ISPSD'98, (IEEE, 1998), pp. 137-140
34. KABAYASHI, K., YANAGIGAWA, H., MORI, K., YAMANAKA, S., and FUJIWARA, A.: 'High voltage SOI CMOS IC technology for driving plasma display panels'. Proc. ISPSD'98, (IEEE, 1998), pp. 141-144