Schottky-clamped NMOS transistors implemented in a conventional 0.8-μm CMOS process

IEEE Electron Device Letters

Volumn 19, Issue 9, 1998, Pages 326-328

  Huang, Feng Jung ^b   Kenneth, K O ^a,b  

^a IEEE

^b University of Florida   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CURRENT VOLTAGE CHARACTERISTICS; SCHOTTKY BARRIER DIODES; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR JUNCTIONS;

SCHOTTKY CLAMPED DRAIN-TO-BODY JUNCTION (SCDR);

MOSFET DEVICES;

EID: 0032165286     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.709629     Document Type: Article

References (9)

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8. S. Peng et al., "A manufacturable 2.0-micron pitch three-level-metal interconnect process for high performance 0.8-micron CMOS technology," in Proc. Symp. VLSI Tech., June 1990, pp. 25-26.
9. R. A. Chapman et al., "A 0.8-μm CMOS technology for high performance logic applications," in IEDM Tech. Dig., pp. 362-365, 1987.