Highly flexible multi-mode system synthesis

CODES+ISSS 2005 - International Conference on Hardware/Software Codesign and System Synthesis

Volumn , Issue , 2005, Pages 27-32

  Kumar, Vinu Vijay ^a   Lach, John ^b  

^a TEXAS INSTRUMENTS   (United States)

^b University of Virginia   (United States)

Author keywords

Adaptable systems; Multi mode synthesis; Reconfigurability

Indexed keywords

COMPUTER HARDWARE; DATA FLOW ANALYSIS; SIGNAL PROCESSING;

ADAPTABLE SYSTEMS; MULTI-MODE SYNTHESIS; MULTI-MODE SYSTEMS; RECONFIGURABILITY;

ALGORITHMS;

EID: 27644469904     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1084834.1084846     Document Type: Conference Paper

References (15)

1. Chiou, L., Bhunia, S., Roy, K. Synthesis of applicationspecific highly efficient multi-mode systems for low-power applications. In Proceedings of the Design Automation and Test in Europe Conference, 2003, 96-101.
2. Van der Werf, A., et al. Area optimization of multifunctional processing units. In Proceedings of the International Conference on Computer Aided Design, 1992, 292-299.
3. Vijay Kumar, V., Lach, J. Designing, scheduling, and allocating flexible arithmetic components. In Proceedings of the International Conference on Field Programmable Logic and Applications, 2003, 1166-1169.
4. Kim, K., Karri, R., Potkonjak, M. Synthesis of application specific programmable processors. In Proceedings of the Design Automation Conference, 1997, 353-358.
5. Guerra, J., Potkonjak, M., Rabaey, J.M. Heterogeneous BISR reconfigurable ASIC's synthesis. IEEE Trans. on VLSI Systems, 6, 1 (March 1998), 158-167.
6. Compton, K., Hauck, S. Flexibility measurement of domain-specific reconfigurable hardware. In Proceedings of the Symposium on Field-Programmable Gate Arrays, 2004, 155-161.
7. Chiricescu, S., et al. Morphable multipliers. In Proceedings of the International Conference on Field Programmable Logic and Applications, 2002, 647-656.
8. Even, G., Mueller, S.M., Seidel, P.M. A dual mode IEEE multiplier. In Proceedings of the International Conference on Innovative Systems in Silicon, 1997, 282-289.
9. Paulin, P.G., Knight, J.P. Force-directed scheduling for the behavioral synthesis of ASTC's. IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, 8, 6 (June 1989), 661-679.
10. Huang, C., et al. Data path allocation based on bipartite weighted matching. In Proceedings of the Design Automation Conference, 1990, 499-504.
11. Park, S., Choi, K. Performance-driven high-level synthesis with bit-level chaining and clock selection. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 20, 2 (Feb. 2001), 199-212.
12. Haralick, R.M., Shapiro, L.G. Computer and Vision. Addison-Wesley, Reading, MA, 1992.
13. Högstedt, K., Orailoglu, A. Integrating binding constraints in the synthesis of area-efficient self-recovering microarchitectures. In Proceedings of the International Conference on Computer Design, 1994, 331-334.
14. Mallon, D.J., Denyer, P.B. A new approach to pipeline optimization. In Proceedings of the Conference on European Design Automation, 1990, 83-88.
15. Karri, R., Orailoglu, A. High-level synthesis of fault-secure microarchitcctures. In Proceedings of the Design Automation Conference, 1993, 429-433.